Author: Paul Bompastore

Company: Unitrode

Title: An Analog Die Size Estimation Tool

Developing a software program to automate the estimation of analog physical die size based only on electrical schematics has always proven to be a technical challenge in the industry.  The challenge is inherent with the nature of analog design which dictates non-uniform structures be laid out.  Also the relationship of attributes on the schematic to define the intent of how structures be laid out are usually lacking.  This is contradictory to digital design, which uses very uniform structures, and provides a close mapping of schematic to physical design.

Recently the Unitrode Tools and Technology group developed a software program that runs interactively in the schematic environment.  The program predicts die size within 15% accuracy.  The tool has been run on more than 20 databases, and has consistently come within 15% accuracy with the majority of times within 10% accuracy.  This paper will present the underpinnings of the tool by describing the device equations used to calculate area along with routing overhead calculations.  Sample layouts will be presented to highlight unique features of the tool.

Author:   Steve Burrow

Company: Cisco

Title: Helpful UNIX commands while designing in Allegro

When designing PCB's in the Allegro platform, I use a number of UNIX commands (awk,grep,sed, etc) to extract and use various information contained in the database. Although many people have "canned" scripts , some don't and can probably benifit from theses little tricks.

Author: Xingang Wang

Company: Harris Semiconductor, Design Systems

Title: "Development of Fastrack RF Simulation Capability Within Analog Artist".

The RF IC implementation requires a new set of CAD tools to cover all aspects of the development process. Unlike traditional discrete RF design, prototyping is practically impossible, and the validation of design can only be done by extensive simulation. However, in order to obtain accurate simulation data to calculate RF performance such as IP3 and 1dB compression point, the simulation must provide a very wide dynamic range for numerical results, which presents a challenge for RF tool development. This paper will elaborate the challenges faced while developing RF design capabilities in the Harris Fastrack Design System, and considerations of UI development for them.

Author: Xingang Wang

Company: Harris Semiconductor, Design Systems

Title:   SpectreRF for RF IC Design

The rapid of growth of the wireless market has created a dynamic environment with an on- going search for lower cost, smaller size, and higher performance RF and IF products.
Traditional discrete designs are quickly reaching the physical limits of size, parasitics and electrical performance. A solution that integrates many RF and/or IF subsystems on a single die promises dramatically smaller size, greater manufacturability and in many cases higher performance. However, the solution for RF circuits provides challenges for CAD tools. CADENCE provides the spectreRF simulator which can be used to simulate RF circuits.
This paper will review some convergence difficulty encountered during the development of the PRSIM wireless local area network (WLAN) chipset at Harris Semiconductor.
The emphases of the paper describes how to achieve convergence with adjustment of convergence parameters.

AUTHOR:     Tony Laundrie

COMPANY:    Silicon Graphics, Inc.

TITLE:      Automatic transistor-level routing with IC Craftsman/Virtuoso using a local-interconnect technology.

A recent Silicon Graphics project involved laying out hundreds of custom standard cells.  To simplify building the cell library, Cadence IC Craftsman was considered for automatic transistor-level routing within each cell.

The IC fab technology chosen for the project had a local interconnect "METAL-0" layer, which could be drawn to connect diffusion shapes to polysilicon shapes without the need for additional contacts or METAL-1. As a result, most of the routing in a cell was done on METAL-0 and POLY, leaving METAL-1 reserved for cell I/O pins and over-the-cell wiring.

Most of the standard cell transistors in the chosen technology were relatively large and usually comprised multiple devices wired in parallel.  IC Craftsman typically expects transistor devices to have metal pins, and any parallel source/drain pieces are expected to be connected ahead of time.  This would have been too restrictive for our cells, causing unnecessary blockages.  Our goal was to let the router decide for itself where to place contacts along wide transistors, and how to connect parallel pieces in order to minimize the amount of METAL-1 wiring.  We encountered some difficulties along the way, especially concerning the mixture of "strong connect" and "must connect" pin shapes on a single device, but eventually we got IC Craftsman close to our goal.

This paper describes how we set up our various parameterized cells and contacts in Virtuoso, and our rule deck and initial "do" file in IC Craftsman to accomplish the task of aggressive routing using a local interconnect layer.

Author: Joe Morrison

Company: Dii Technologies

Title: Extending Allegro, Revisited

  Allegro is a powerful tool for designing printed circuit boards, but it does not necessarily have all of the features that you want or need. This presentation will discuss a number of different ways that Allegro can be customized to work better with you – such as scripts, Skill, menus, and toolbars. Although much of these topics are pertinent to the Allegro "Classic" GUI, the focus will be on leveraging and customizing the new windows based GUI.

This presentation revisits the Extending Allegro paper presented at ICU 95 and updates it for the new GUI introduced by Cadence. In addition, issues related to supporting both Unix and NT workstations have been added to this presentation.

Author:   Julia Perez

Company:     Motorola SPS  

Title:  Parameterized Device Level SKILL Procedures

Device level procedures were developed in an effort to decrease the development cycle time of parameterized cells. The device layouts are defined by typical design spacing relationships instead of geometric shapes. The device layouts and parameterization requirements of several different technology libraries were examined for similarities. The procedures methodology can accommodate capacitors, diodes and bipolar devices and new parameter features such as guard rings. The procedure keywords are represented in a GUI or in a SKILL text file. The MOS transistor, MOS series transistor, and resistors are presented in this paper.

Author: W Y Liu

Title: Pcell Realization of Novel Microstrip Filter structures For Millimeter Wave or Microwave Frequencies.

This paper presents a Pcell approach of microstrip bandpass filter realization based on a novel topology. The filters realized with this topology are intended  to operate at millimeter wave or microwave frequencies, with symmetric passband bandwidth exceeding 100%. Unlike most commercial filter synthesizers, whose output is no more than a filter schematic, a Pcell generator as such can not only allow rapid realization of RF filters, but also symbolically generate an S-parameter matrix that can be readily used in any RF receiver design.

Author: Gemma Gylling

Company: Cisco

Title:  How to Setup Virtual Pins in Allegro and Pass it to Specctra

This paper will explain how to set up Delay Rules in a "Star" or "H" topology, using virtual pins, in Allegro and passing those rules to Specctra.  I will show how Specctra accepts the rules and how it routes the nets.

Author: Gemma Gylling

Company: Cisco

Title:  Tandem and Parallelism Rules between Allegro and Specctra

This paper will explain how to set up Tandem and Parallelism rules in Specctra.  I will then explain how to check for both tandem and parallelism in Allegro and an easy way to go about fixing the violations, in Allegro, as well

Author: John F. Lane

Company: OHIO Design Automation, Inc

Title: GenCAM Intelligent CAD to CAM Transfer IPC 2510 Standard

GenCAM, the IPC's latest standard, provides an ASCII file format by which PCB CAD data can be intelligently delivered to the CAM world.  The GenCAM file format supports the definition of one or more PCB CAD designs in a single file.  All aspects of the Allegro design may be captured in this ASCII file.  GenCAM describes Allegro's layers and colors, as well as pads, padstacks and components.  Shapes (planes) connect lines, vias, and pins, are all represented.  Test pins, mechanical features, board outline, silkscreen and format geometry are all represented.

Once the design is output from Allegro, CAM software may check for potential manufacturing flaws and develop optimal panels.  Test fixtures may be designed based on the GenCAM information.

This paper will describe the various sections of the GenCAM file and how various sections may by utilized in a more intelligent CAD to CAM data transfer.

Author: Vincent Lau

Company: Conexant System, Inc

TITLE: Use of inherited connections in stdcells library

The introduction of inherited connection in Cadence's 4.43 release proved to be very useful in the usage and deployment of stdcells library.  This new feature shorten our CAD development time in several areas: (1) Individual symbols don't need to be edited for power and ground pins, (2) Schematics underneath the symbols do not need power and ground pins added, (3) Designers using this stdcells library don't need to wire the default power and ground pins. A more detail example of the implementation using inherited connection is presented and the benefits are explained.

Author:   Ed Gilbert   

Company: Infineon Technologies, Corp.     

Title: Experience with a Cadence-based Mixed Signal Design Flow

Infineon's Read Channel Design team, based in Santa Cruz, California, created a mixed-signal IC for disk drives that operates with clock speeds greater than 500 MHz and includes sensitive analog circuitry.  The digital portion consists of standard cell gates and several large datapath blocks. 

The simulation environment consisted of the Spectre and Verilog simulators, either stand-alone or together using spectreSVerilog.  The analog and digital sections used different simulation strategies to verify lower level functionality, but as the design neared completion, all analog, digital and mixed signal simulations were run from the same schematic. 
The digital strategy implemented Verilog-RTL and gate-level to simulate all aspects of the digital design, while the analog strategy created schematic, extracted macro-model and Verilog -A views for all blocks.  Some of the more digital analog blocks (plls) also had a Verilog view.  Using the Hierarchy Editor, it was possible to run Spectre with any combination of the defined views to ensure a robust design. 

All top-level simulations were run from a chip-level schematic that included the pads.   The digital designers could run a straight Verilog on the design using the defined test ports and the Verilog pll description without other analog descriptions.  The analog designers could simulate the analog portion from the same schematic using Verilog-A stimulus that reads pattern files created by the Verilog designer's simulations.   Finally, a true mixed signal simulation was done using the Hierarchy Editor to mix and match the different analog views.   |

Author: Christopher Day and Carl Musetti

Company: General Instrument Corporation

Title: Concurrent Design Environments  (Blending NT into and existing UNIX infrastructure)

An increasing problem companies face with regards to CAD tools is working with NT and UNIX based CAD tools, which most often have completely different system infrastructures and design methodologies. One major dilemma is how to incorporate NT CAD tools into an existing UNIX infrastructure without the exhausting effort of maintaining duplicate databases, libraries, and re-coding custom scripts.

Results from testing by the Design Automation group at General Instrument Corporation show that UNIX scripts can be launched from NT, executed on UNIX and any GUI can be displayed back to NT. This makes the actual operating system being accessed transparent to the user. CAD databases and libraries are accessed from NT through an NFS gateway, which connects the UNIX drives to the NT network. NFS gateway software offers permission synchronization for direct compatibility between NT and UNIX.

The goal here is to maintain a Client/Server infrastructure, allow companies to implement NT into their established UNIX environment, and access only one design and library database, all without redesigning an existing design methodology. Customized UNIX scripts can also be utilized, even if they have not been written in a platform independent language, such as PERL. This will not eliminate the basic need to re-write scripts, but it will save a company hundreds of hours of re-coding during the initial NT/UNIX integration and rollout phase.

Author :     Di Phan

Company:     IBM

TITLE   :  A CUSTOM DATAPATH DESIGN METHODOLOGY

This paper describes a custom integration methodology for a highly irregular and complex datapath macro design. The methodology made use of an integrated customized Skill-based floorplanning and design verification toolset which can support any user-specified bit image pattern.  Critical features of the implemented methodology include an integrated design database, automatic macro pin placement, algorithmic wiring blockage and power grid generation, plus design consistency checking tools which are all tailored to support datapath designs.

Author :     Di Phan

Company:     IBM

TITLE   :   ROUTING CHALLENGES ON A RE-ENGINEERING PRODUCT

This paper describes some shortcomings of existing autorouters when they are used on a microprocessor design which was mapped into an advanced CMOS technology with more than five layers of metals. Areas of routing difficulties include the handling of special routes involving wrong-way wires, asymmetrical vias, fat and/or crosstalk wires.

Author: Stephen G. Brickles

Company: Elantec Semiconductor Inc

Title: Using The Analog Workbench for IC Design

Traditionally, the Cadence Analog Workbench is used for PC Board Simulation and Design, however the flexibility of the software allows it to have applications in other design fields as well.  A methodology for using the toolset in an IC design flow and a description of how it may be customized for this application will presented along with real-life examples.

Author: Stephen G. Brickles

Company: Elantec Semiconductor Inc

Title: Customizing The Analog Workbench and Concept

Customization and scripting techniques will be demonstrated, including adding node numbers to schematics and working with external simulators such as OrCAD PSpiceí.  A method for speeding up compilation time by rewriting model templates is also presented as well as some useful utilities for plotting and archiving.

OrCAD PSpice is a registered trademark of Orcad Inc

Author: J. Marc Edwards 

Company: Cisco Systems, Inc

Title: RTL Based Object-Orientation Modeling Using NC-Verilog & 'E'

The object-oriented programming (OOP) paradigm has gained substantial acceptance in the realm of software engineering.  System designers/architects can now take advantage of the OOP for hardware architectural descriptions.  If Verilog can be described as an RTL extension of 'C', then Verisity's 'E' language can be described as an RTL extension of JAVA.  Using 'E', a system designer/architect can model and specify, using the OOP, any logical hardware based architecture with efficiency and enhanced productivity.   The modularity and conciseness imposed upon the system designer provides for an object-based design description that can be used and extended throughout the life of the architecture.  The 'E' language also provides 'built-in' constructs for data generation of objects (lists of transactions, frames, cpu instructions, etc). This allows for rapid stimulus generation into the object-based description with the NC-Verilog simulator.  The proposed paper will outline how the 'E' programming model fits in with the NC-Verilog simulation environment, and how a hardware based architecture can be rapidly modeled using an "RTL-object-oriented" programming language that is designed to interact with the NC-Verilog simulator.  The 'E' based object model can then be "translated" into a working Verilog implementation.  Just as only a subset of the Verilog language  is "synthesizeable", a subset of the 'E' language can be defined as "translatable".  The automation of the "E-2-Verilog" translation process will further enhance the validity of the object-based hardware description, and allow hardware architectures to enjoy the clear advantages object-based descriptions and programming.

Authors -   Thomas Wohlfahrt and  Keith Barkley

Company: IBM

Title  -   Hierarchical Methodology, Contract Generation and   Layout Abstraction (blockage modeling)

   One of the  major benefits of hierarchical design is the ability to do concurrent design on the various levels of hierarchy. One of the items that must be properly managed is the utilization of wiring resources between the levels of hierarchy. If this management is not done properly, then hierarchical design can actually become detrimental. The methodology for the management of wiring resources is based upon the concept of contracts. Contracts partition a level of hierarchy with another level of hierarchy to designate the wiring resource used by each.   Complex layout abstraction and blockage modelling is essential for achieving a "correct by design" error free design approach. The design layout rules are evolving at such a rapid pace that the automatic tools cannot handle many of the detailed shape to shape relationships and constraints. Manual corrections for DRC/LVS violations are at times difficult or impossible to implement.

  A  Cadence DFII , skill/diva based code environment was created to achieve the proper modelling that results in an "error free", "correct by design" chip layout. The S390 G5/G6 Custom Microprocessors were successfully designed using a version of this code.

Author: Robert D. Morel

Company: IBM

Title:  REPTILE - REPository of Tools, Interfaces, and Other Local Enhancements

Abstract:  REPTILE is an acronym for REPository of Tools, Interfaces, and other Local Enhancements.  The primary objective of such a repository is to make Skill applications generally available to the design community without having to modify initialization code at either the project or user levels. REPTILE is a completely self-contained point tools environment, complete with a graphical user interface.  This interface simplifies the development and maintenance efforts for application engineers, and provides an easy way for designers to access the custom tools repository.  Initialization of the REPTILE environment is established via a single load command in the .cdsinit file.  Startup time of the REPTILE environment is minimized through extensive automatic autoloading.

Title: HP EEsof-Cadence RFIC Integrated Design Flow

Authors: Mario Aranha, Michael Burt, Xingang Wang*, Mark Williams**

Companies:   *  Harris Semiconductor         ** Cadence Design Systems

This paper provides an overview of the integration of HP's Advanced      Design System(ADS) with Cadence's IC Design Framework (DFII), in what      we call the Integrated Design Flow(IDF). The integration is based on      OASIS Netlisting and Inter-Process Communication, ensuring design data      integrity. Important aspects of the architecture, use-model,      underlying technologies and library customization will be presented.

Title:  Advantage Micro-Via

Author: Tom Morris

Company:  KAW Design Inc.

     This author presented on Micro-Vias to this body one year ago.   Since that time many things have changed, although some have not.  Issues in the not changed category include excessive misinformation, a lack of understanding the real value of this technology and a reluctance to commit designs due to real or perceived barriers in manufacturing.  The two largest manufacturing barriers include real verses claimed capabilities and excessive pricing.  The good news is that more designs aare using this technology even though it is usually only in selected areas of the board.

     To be discussed is a project where each of eight designs used micro-vias exclusively.  Each board contained several BGAs of 208 to 726 pins and several SMT devices containing up to 356 pins on .5 MM or less pitch. With only two micro-via layers we were able reduce six layers per board using a one step lamination process, standard material and achieve a price significantly less than the originally quoted board using traditional thru-hole vias.  We will discuss the design methodology, the feature sizes and layer stackups, a comparison of routing densities, and how this technology impacts Allegro/Spectra. 

As we discuss the merits of Micro-Via design methodologies, we will also discuss the limitations and where this technology achieves the most impact. We will discuss future trends for high density interconnect (HDI) including the photo-defined (Build-up) process and where CAD limitations may occur.   

Author: Peter Dudley

Company: IBM

Title: Multi-Site Microprocessor Auditing and Data Management Methodology

As microprocessors increase in size and complexity, the auditing and data management of their physical design becomes increasingly complex and interdependent.  Auditing and data management also become more essential to the success of completing the designs of these new microprocessors. This paper presents the core of the "Multi-Site Microprocessor Auditing and Data Management Methodology" currently being used by a large multi-site design team to develop a leading performance microprocessor for servers. Our physical design environment includes Cadence integrated with a multitude of point tools.  A brief history of our methodology, the critical issues we were confronted with, and how we are dealing with them will be addressed. 

Author:: Mark Gloster

Company: 3Com

Title: PCB Futures: Successful PCB Design for the New Millennium

This paper is less about specific tool use than about shifts in technology, and addressing those as a PCB designer or design organization.

I. A Quick PCB Design History
II. Technology Overview    
A. Current Model          
1. Electrical          
2. PCB Fabrication          
3. Assembly/Test          
4. Time to Market     
B. Trends (The Sky is Falling)          
1. Manpower          
2. Electrical          
3. PCB Fabrication          
4. Assembly/Test          
5. Time to Market
III. Mechanics of Addressing Future Requirements     
A. Electrical Design     
B. Fabrication     
C. Assembly/Test     
D. Time to Market     
E. Tools of the Trade
IV. Challenges     
A. Untried Technologies     
B. Communication     
C. Competition     
D. Corporate Politics     
E. Geography
V. Success     
A. Communication     
B. Expanding Knowledge Base     
C. Tools of the Trade     
D. Partnering     
E. Service     
F. Evangelism

Author: Mihai Lita

Company: Catalyst Semiconductor, Inc.

Title: A DFII Block Extractor from a Multiple Circuit Descriptions Environment Targeting the SILOS III Simulator

Mixed EDA environments are sometimes imposing "custom" interface development to maintain the integration of tools within acceptable limits.   The paper is describing such an interface - a block extractor - needed to integrate a simulation environment - SILOS III - into the design flow.  The input data for this simulator has to be extracted from the DFII database, built using the Composer tool. Since SILOS III is accepting several input data standards - IEEE P1364 Verilog + a unique (Simucad) analog extension helpful in analog behavioral modeling, SDF, PLI,  HDL,  Simucad proprietary primitives for netlisting, an appropriate interface was developed to take advantage of simulator's features.  A cell / block can have either one or more such descriptions. This interface is covering both the physical circuit description, based on standard primitives, hierarchically built through Composer schematic entry functions and the formal module descriptions, based on behavioral models and/or other text oriented block-descriptions. All these descriptions are integrated into the DFII environment.

Author: Mihai Lita

Company: Catalyst Semiconductor, Inc.

Title: DRC Deck Rule Splitter & Builder of a User Specified Rule or Set of Rules

In the physical verification process, there are sitiations when the designer is interested in only a particular rule or sub-set of rules. In these cases running the entire deck - full  set - of  DRC rules is a waist of time. The paper is presenting a DRC rule splitter and, based on the user choice, a rule or sub-set of rules deck builder, that enables the layout designer to focus on a specific set of changes. This specific DRC rule builder  is useful also in technology development investigations, when only one rule - seldom a few rules - is involved in evaluating the correlation between layout structures -measurements, or in estimating marginalities when a fast feedback is needed. Timing considerations are discussed. A DFII interface is provided through which the user can setup the options.

Author: Leigh Eichel

Company: Valor

Title: Automated DFx ( Design For Excellence ) review

This paper will explore emerging methodologies and field proven solutions in concurrent design for Assembly,  Testability, and Fabrication. .  It will provide an overview of the high level of integration between Cadence Allegro and the Enterprise 3000 manufacturing simulation software.  This paper describes how factory based rules are implemented into the design process providing true value added engineering solutions for Allegro users.  By verifying the producibilty at the design stage, designers can reduce time to market and eliminate revision spins.  Additionally, methodologies will be reviewed for Gerberless data transfer to manufacturing.

Author: Donna J. Ducharme

Company: Unitrode Corp.

Title:Installation and setup Of the "C" based Interface From Virtuoso to IC Craftsman; A User's Perspective

I will explain the process we went through to replace the skill translator to the C based translator in 4.3.4.  There will be a discussion of the post processing we had in place prior to the transfer.  Covered will be what we could leverage from this new translator, and also  how the post processor was modified to support the new translator.  Also included in this discussion will be the approach taken to minimize the impact to layout.  The paper will identify technical problems encountered with the upgrade, and short term work arounds along with long term plans for permanent solutions.

Finally I will show what we ultimately achieved in the 4.4.3 environment with an outline of the differences from the 4.3.4 environment.

Author: Neel Pandeya and Arthur Schloth

Company: Teradyne Inc.

Title: "Dynamic PLI-Controlled Simulation Enables Concurrent IC Design And Test Development"

Test simulation leverages EDA tools to allow for the concurrent development of design and test. A test program interacts with electrical models of the Automated Test Equipment (ATE) instruments and the Device Under Test (DUT). Test Simulation provides benefits for the entire IC product development team, such as:

• improved time to market - faster design and test development cycles
• concurrent device design and test development
• additional device model debug, before first silicon
• test package validation, before first silicon
• reduced on-line silicon debug time

VX is Teradyne's family of test simulation products. SpectreVX and DigitalVX/Verilog-XL integrate Teradyne's ATE test program development environment with Cadence EDA tools to provide a "closed loop" simulation of the tester environment.

Specifically, this paper will describe:

• the architecture of VX
• Teradyne tester model development using Verilog and SpectreHDL   within Design Framework II
• the VX netlisting process
• the use of the Verilog PLI to control simulations dynamically   from within Teradyne's test program development environment
• incorporating the user's DUT into the VX simulation environment
• several VX customer success stories

Author : Sean W. Smith

Company: Cisco Systems Inc.

Title  : Transaction and Data Driven Verification

Abstract:  With the ever evolving complexity of today's digital systems, functional verification has become an increasingly difficult challenge and time consuming task.  New methods and techniques must be applied to effectively verify these systems and accomplish the task in a timely fashion.   There are several key techniques which are quite powerful by themselves but when combined provide the verification engineer with a complete arsenal of tools for attacking this problem.  The key elements of this approach are:  A. Robust, Fast, and Flexible Event/Cycle Simulator B. High performance modeling of memories C. Object Oriented Directed Random Test Generation and D. Code coverage analysis.   I will discuss each of these topics briefly and then show how they can be used together as a system.  These techniques can be applied to ASICs, FPGAs, system on a chip, and PCB's.  The key benefits of this approach are flexibility, early detection of bugs, reduced verification schedule, and reduced time in the lab with first hardware.

Title: Stretchable Pcell Functionality in the Virtuoso Layout Accelerator

Authors:    Randy Bishop,   Rose Mary Soto, Jeff Barber, & Shelly Evans

Company:    Cadence Design Systems   

Stretchable pcell functionality provides users with a quick, new way to graphically update pcell parameter values using the Virtuoso layout accelerator Stretch command.  The often tedious and iterative process of calling up a form, changing parameter values for a pcell on the form, applying the form, and checking that resulting shapes are correct, is replaced with an interactive, graphical command that provides instantaneous graphical feedback.    Stretchable pcell functionality is implemented using Relative Object Design (ROD) constructs defined in SKILL pcells.  A new function, rodAssignHandleToParameter, associates a ROD stretch handle with a pcell parameter.  Stretch handles can be displayed graphically as small diamonds.    To "stretch" a pcell, the user starts the Stretch command, selects a stretch handle, and moves it. As the stretch handle moves, the values of the pcell parameters assigned to that handle automatically update. The drag set displayed on the screen contains the shapes the pcell's SKILL code generates from its newly updated parameter values, so the pcell appears to "stretch" as the cursor moves.  By default, parameter values update when the cursor moves.  However, the user can take complete control of how parameter values are updated by specifying a user-defined function.    This paper describes  the definition, use model, and underlying implementation of stretchable pcells. Several examples, from simple to complex, are provided including an example that shows how to graphically change contact coverage of a mos device.

Title: An experience using Inherited Connections in the CICI mixed-signal design flow

Co-authors: Udi Landen & Dzung Tran

Companies: Cadence Design Systems, St Jude Medical

Moving into SOC and DSM era, the need to have multiple supplies increases in order to satisfy different types of designs such as: multiple-voltage designs, mixed-signal designs, high speed designs with quiet substrate, etc.

When building a standard cell library to be used for these designs, the question of having implicit or explicit power pins is very common. Neither ones completely satisfy different requirements by designers and library developers:

For the analog designers, explicit power pins are a must so they can specify the power connection from the lower level of the hierarchy. On the other hand, the digital designers don't want to see the power pins until the higher level of the hierarchy. The layout designers would like to see an easy-to-read schematic and to be able to verify the proper power/ground connections. Library developers wish to reduce the effort of developing/maintaining the library either due to the limited resources or the growing list and complexity of the CAD tools to be supported by the library.

This paper presents our experiences using Inherited Connections to build a standard cell library and then using this library throughout the CIC mixed-signal design flow.

Author: Christophe Bianchi

Company: Frequency Technology

Title : "Integrating Inductance modeling in a Cadence verification flow"

Columbus Inductance Modeler is the industry's first solution for modeling inductive effects on sub-quarter micron designs. Introduced by Frequency Technology in May of 1999, Columbus Inductance Modeler^TM drastically improves the accuracy of circuit performance analysis by combining the modeling of inductance effects with the modeling of resistance and capacitance of high-performance interconnects. This new technology is now fully accessible in the Cadence flows through a set of interfaces. These interfaces provide full integration into both the Dracula, Vampire and the Silicon Ensemble flows, providing the Cadence users with the complete inductance modeling capability of Columbus. This paper first discusses the impact of inductance on today's high-end integrated circuits, highlighting the impact of inductance on timing, and thus showing the need for an accurate modeling of inductance as part of the final design verification process.

A real-life example is then used to describe the inductance modeling process, which allows the user to detect a degradation of circuit performance as high as 32 %. More examples are presented that highlight the effect of different parameters such as design style, process, interconnect material and circuit performance on the inductance. Finally, the integration with the Dracula, Vampire and Silicon Ensemble flows are outlined, with an emphasis on the ease-of-use and ease-of-setup of this solution.

Author: Paul Mason

Company: Cadence Design Systems

Title: ACPD what is it?

This would be a talk descibing Cadence Assisted Custom Physical Design flow. The tools involved as well as the features and effects of using a design flow. The talk would cover Composer-VirtuosoXL-ECHO-IC Craftsman.

Title: Nonmonotonicity in Timing Libraries

Author: Kambiz Rahimi

Company: Cadence Design Systems

Nonmonotonicity appears naturally as more abstract timing models are derived from transistor level circuit simulations. The magnitude of differences among nonconforming values are generally small but they make the algorithmic circuit optimization more difficult. We present a detailed account of this effect and a way to alleviate the problem by filtering out the nonmonotonicity for timing driven tools. The algorithm discussed here has been implemented and is in use in a Cadence services project.

Author: Paul Musto

Company: Cadence Design Systems

Title: HDI (IC Packaging)

This presentation will provide an overview of new methodologies and tools that address both the physical and electrical optimization of today's complex IC packages. Specifically, IC & Package integration, package physical design, signal integrity, and PCB design model generation will be discussed.

Author: Todd Westerhoff

Company: Cadence Design Systems

Title: Source-synchronous Bus Design

As buses go beyond 100 MHz, design will transition from conventional "common clock" techniques to the newer scheme of source synchronous data transmission. This paper examines how source-synchronous techniques affects PCB design and signal integrity analysis.

Author: Ron Matthews

Company: Cadence Design Systems

Title: PCB Design for the Mitigation of EMI

The successful design of high-speed printed circuit boards has always required that numerous problems relating to signal integrity be addressed. These problems are of immediate concern as they directly impact funtionality. However, an equally serious problem is that of designing PCBs for the mitigation of Electro-Magnetic Interference (EMI). EMI is not a single problem but is rather a term which refers to a collection of electromagnetic phenomena, any of which can cause a system to fail to meet international Electro-Magnetic Compatibility (EMC) regulator limits. This tutorial provides a brief overview of the international regulatory climate related to EMC, a look at the types of EMI problems that can be caused and cured in the PCB and introduces a few of the design methods that can be used to mitigate EMI by design.

Author: Kishore Karnane

Company: Cadence Design Systems

Title: Analog RF

The presentation on Analog RF for ICUG will provide solutions to the technical challenges of RF designers who are mixing high-speed digital, analog and RF circuits. It will also highlight the architecture as well as UI of the Analog Simulation capability on NT for PCB designers. The next generation of AWB.

Author: Carlos M Roman

Company: Cadence Design Systems

Title: A Hierarchical Verification Methodology

This paper describes a hierarchical verification methodology using model checking technology. The methodology introduces model checking early in the design cycle in order to minimize the overall verification effort. It relies on the design's built-in hierarchy as the mechanism to conquer its complexity during verification. The methodology minimizes state explosion problems by concentrating the bulk of the verification effort to RTL-Level modules suitable for model checking. An assume-guarantee paradigm is used to verify functional units built on top of instantiation of previously verified RTL-level modules. Therefore, the verification process follows a bottom-up approach tracking the development of the RTL-level code used to implement the functional units embedded in the design.

Benefits of the verification methodology described in this paper include:

• Complete verification of RTL-level modules and their interfaces.
• Complete verification of functional units implemented with    instantiations of previously verified RTL-level modules.
• Complete verification for the design's top-level properties    directly mappable into verifiable embedded functional units.
• Early identification of target areas within the design for which    simulation or alternative solutions are required.
• Higher confidence on the functional correctness of the design.

An example of this methodology is fully presented using Affirma/FormalCheck, the model checking solution commercialized by Cadence Design Systems, Inc.

Authors: Kenny Furguson and Kenny Mackie

Company: Cadence Design Systems

Title: Envisa Abstract

Picasso is the new cell and library preparation tool that takes physical layout design and the design rules, produces full-shape abstracts for the cells and macro blocks in the library.  This tool is integrated with the DSM design database. The abstracts are tailored to Cadence placement and route system.  This tool provides better usability and simple flow so that the libraries, blocks and cells can be easily, quickly and accurately modeled.

AUTHORS: Sumeer Goyal & Nikhil Gupta

COMPANY: Cadence Design Systems

TITLE: MANAGING DESIGN AND LIBRARY DATA IN CADENCE INTRICA ENVIRONMENT

Increasing design complexity, and shorter time to market has resulted in multiple designers working on the same design simultaneously. Teams are also distributed around the globe to take advantage of the local geographical factors. To avoid one designer's changes to be overwritten by another designer, for isolating "what-if" design scenarios and for effective sharing of stable data, it is imperative to have data management built into the solution.

Also, a user moving from a non DM environment to a DM environment should not experience any major changes in the methodology. Otherwise, a lot of resistance would be encountered with the users.

A Data Management (DM) solution has been introduced in the PE tools in the PE13.6 release, using the Cadence GDM (Generic Data Management) API. This solution allows the user to work with any data management system (after an initial setup) - hence the term "generic". A new graphical tool "designmanager" has been introduced that allows a  designer to manage his design data from within the Cadence PE Project Manager. In the library space, the Library Explorer manages all the data management interactions. As a result, the existing tools such as ConceptHDL, Packager, Allegro, Part Developer remain unchanged.

This paper is going to introduce the PE DM solution to the audience, and will talk about how DM requirements are solved both in design space as well as library space. It will also indicate how the solution can work with any DM solution, and how the user's design/library methodology would remain almost unchanged with the introduction of a DM system

AUTHORS: Satinder Sood, Pankaj Chawla, B Shreeharsha, & Nikhil Gupta

COMPANY: Cadence Design Systems

TITLE: Concept HDL based Programmable IC Flow

The improved mixed level support to the ConceptHDL based PIC Design environment in PE 13.6 provides a tight integration between ConceptHDL, Synplicity's Synplify (FPGA/PLD Synthesizer) and third party FPGA/PLD vendor P&R tools (Xilinx, Actel and Altera). It also provides a complete design flow for designing FPGA/PLD devices and integerating the implemented devices seamlessly into the boards.

The PIC flow starts with entry of the design.

The user Has the choice to enter the design as only schematics (bottom up flow) or only HDL blocks (top down flow) or a combination of both (mixed level flow).

Has the flexibility to use both Verilog and VHDL blocks in the same design.

Is not restricted to write HDL files in a particular structure ( like one module per file ) These files are then imported into 5x structure. The HDL import step also creates Concept symbols for each of the modules in the HDL files which can then be used in a Concept schematic.

The center piece of the new flow is the design partitioner that partitions the design into schematic, HDL blocks, user pre synthesized blocks and macro cells created using vendor tools.

The schematic blocks are then netlisted into edif for the target vendor P&R. The HDL blocks are processed through Synplify to get the edif files for P&R tool.

All the edif files are finally gathered into one run directory for the P&R tool.

Since partitioning breaks the design into schematic, Verilog and VHDL blocks and each of them is processed seperately, one can design using a combination of all three. Also because of different processing for each of them, all vendor properties that may have been specified in the blocks are preserved.

After partitioning and netlisting each of the sub-blocks into edif files, the vendor P&R tool is invoked.

A unique feature of the flow is that a custom device for the FPGA is created, which can be directly instantiated in the board level schematic.

At various stages, the user has an option to do simulation (functional, post synthesis and timing) for the whole design. The flow provides a high level of integration with simulators like Verilog-XL, Leapfrog or any third party simulator.

Author: Juergen Hartung

Company: Cadence Design Systems

Title: Parasitics & RF Design

EDA is of great importance for the microelectronic industry. Beside the state-of-the-art process technologies, the circuit and system know-how, the design flow/methodology is a key requirement for success. To meet the challenges due to System-On-Chip (SOC), sub-micron technologies and the so called Design-Gap introduced by advancements in process technology, a closer relationship between Systemhouses, IC-Houses, Research Institutions and EDA companies is necessary. In Germany, one strength of the electronics industry is mixed-signal and analogue design with a focus on communication and automotive applications.

Therefore Cadence Design System GmbH, Germany, has joined two consortiums of leading European electronics companies and German technical universities. In the first, an advanced methodology for wireless system architecture and Radio Frequency (RF) design will be developed. The second project investigates parasitic effects, their impact on design performance and their consideration during the design process. Although Cadence provides comprehensive tool and flow solutions, some company-, application- and technology-dependent adjustments are frequently necessary. In the projects, Cadence will help the partners to find the best solutions, that they can use the results in the Cadence environment. Other advantages of such consortiums are user feedback, tool
evaluation, beta-tests and comparison against silicon for the provided solutions.

The paper will describe the scope of the projects, Cadence existing tools/flows in this area and enhancements to the provided solutions developed in the projects.

Author: Sumit Arora

Company: Cadence Design Systems

Title: Performance improvements in DFII Verilog Import

Importing a verilog design to DFII environment forms an integral part of many design flows since it is easier to debug and edit schematics as opposed to text. The verilog import tool creates CDBA schematic and netlist views from verilog netlist. The imported CDBA database is also used to drive many physical design tools.

Increased design sizes and the observed time for importing designs led to many demands for speeding up the tool. Changes have been made so that the tool generates CDBA Netlist views upto 40 times faster. It has been enhanced to generate compiled versions of verilog libraries to save compilation time of the same libraries again. Going forward we further plan to reduce the CDBA schematic creation time and enhance the placement and routing module used to generate schematics.

The paper will talk about the speedup initiative for verilog import, the steps taken and the results achieved. It will give details about the limitations of the tool and certain tips and tricks to import designs faster and to get around some of the limitations. It will also outline the future development path for the tool.

Author: Sumeer Goyal

Company: Cadence Design Systems

TITLE ----- Enterprise Wide Design Paradigm for Cadence PE Environment

Today's complex design methodology demands a tight integration between electronic design activities and  other aspects of business of an enterprise.

For example, designers can no longer afford to choose a part just on the basis of its schematic shape or package properties. They need access to as much part information as possible upfront before selecting a part. Information such as procurement cost of the part, its availability and status, vendor information, lead time (and much more) help the designers make better design decisions. This in turn leads to lower design costs, less number of design iterations, and shorter time to market. Such part information is available from different processes in the company such as design, procurement, components, and manufacturing.

When different processes in the enterprise are co-operating and sharing information with each other to achieve the common design realization goal - we call it the "enterprise wide design paradigm". Information that is shared between team members is accurate, and up-to date. Customers can access this information without having to leave their design environment.

In this paper, we are going to introduce the concept of the enterprise wide design paradigm. We will talk of the benefits that our customers will reap from this paradigm. We will define the enterprise solution in the context of Cadence PE toolset and talk about the specific functionalities that make it up. We would update the customers on the current status of this new paradigm.

Author: Laurent Thenie

Company: Cadence Design Systems

Title : Process Antenna Effects Verification Using Cadence's Dracula of Vampire Physical Verification Tools

In today's DSM technologies, the ANTENNA effect has become a major issues that must be addressed during physical verification. With the reduction of gate length (0.35um, 0.25um, 0.18um..), it is important to be able to accurately check the Antenna effect to avoid gates destruction during wafer processing. We will discuss the differents models which exist : "cumulative/non cumulative models" as well as the parameters which have to be taken into account to get correct results. We will demonstrate as well that Cadence tools involved in Antenna rules verification offer a coherent approach (Silicon Ensemble, Dracula, Vampire) Typical rule files will be commented.

Author: Uma Mudumba

Company: Cadence Design Systems

Title : Timing library enhancements for Signal Integrity and Reliability

With the advent of very deep submicron technology, EDA vendors need to provide solutions for the signal integrity and reliability issues. Libraries which thus far contained timing information only need to have power as well as Signal integrity information. 

Timing Library Format (TLF) is the Cadence proprietary format used by most of the DSM tools like SEUltra, CTE, Power Analysis, CTGen, UltraPlace and Xtalk in DSM flow to access library cells' timing information. TLF has been enhanced to cater the requirements arised from the inclusion of signal integrity and reliability calculations in the DSM flow and to make more informative than other library formats like Synopsys .lib, ALF and DCL.

The following factors, which affect signal integrity and reliability calculations, are taken into account to enhance TLF  

• Crosstalk :       Cross coupling with the adjacent segments may cause incorrect logic       levels and affects delay.  
• IR Drop:        When large current is drawn, the IR drop at the power        supply or ground wires alters cell function.   
• Electromigration :        When current density in power supply segment is high, the long term        stress of unidirectional current leads to segment destruction.   
• Hot Electron :        When large electric filed exists, the fast electrons in the        channel causes threshold shift and mobility degradation.

This paper describes the way the signal-integrity and power related library parameters, which characterize the above factors, can be represented in TLF and set of API calls to integrate the enhanced TLF into various DSM toolset which are targetted for the upcoming POMPEII release.

Author: Sandeep Srivastava

Company: Cadence Design Systems

TITLE: Year 2000 Compliance in Stream Files and PIPO

Stream Format is a very widely used Cadence owned format for storing design data and is used for transferring design data between companies, sending the final design to the Fab, or archiving design data. Due to its wide usage, it is very important that it be Y2K compliant.

Dates are used in stream files in two records - BGNLIB (Begin Library) and BGNSTR (Begin Structure). Stream Format reserves two bytes for each one of the years in the dates in BGNLIB and BGNSTR records. These two bytes can be used to store years upto 32767.

On UNIX and Windows NT, there are two standard ways to represent time - time_t and struct tm. struct tm is a C structure with fields for year, month, day, and others. The years fields in struct tm is defined as the number of years since 1900. Hence 1999 is represented by 99, 2000 by 100 and 2001 by 101 and so on. PIPO stores the date represented by struct tm directly in the stream file with a minor modification to the month.

We considered changing the year format to store the actual 4 digit year in the stream file. However, since struct tm is one of the industry standard Y2K compliant formats to represent dates, and since a change in the date format would cause a big problem for other tools and scripts that read or write stream files and are used to dates represented in the current format, we decided to keep the year in the stream file as it is.

In Streamin, the date from the stream file is read into a struct tm and then the mktime and ctime C library functions are used to print it.

We recommend the above methods of storing and reading dates in stream files. However, for tools that haven't migrated to this recommended methodology, Streamin will still be able to read in dates in most of the other likely formats written by such tools.

Author: Anil Bhatnagar, Rajan Arora, Narendra Jain

Company:   Cadence Design Systems

TITLE:  Performance enhancement initiatives in Virtuoso(R) Stream Interface

PIPO is a set of translators used to translate mask layout data from Design Framework II database format to Stream, CIF, Applicon & CALMP formats. It is an important interface used by almost all the users of Virtuoso(R) Layout Editor worldwide.

Due to increasing design sizes, users have been asking for improved speed performance and lower memory requirements in the Stream Interface. R&D has taken a number of initiatives in the ongoing Apache release to enhance the performance of  STREAMIN and STREAMOUT.  Basically, we started with two activities in parallel. In the first one, a prototype of STREAM IN and OUT was quickly developed with the aim of some major performance enhancement. In the second approach, we carried out rigorous performance analysis on the exisiting code (using quantify and then extensive architectural analysis of code) to find out major performance bottlenecks and also code segments which could be potential candidates for improvement.

The prototype has demonstrated upto 4x speed improvements in certain cases. The work on the performance analysis of existing code is underway and has already helped to identify some crooked segments/bugs downgrading tool's performance by 2 times in some cases. Findings of the above approaches have been planned for the Apache release.

This paper will discuss the techniques used to achieve these enhancements, the suggestions identified for dependent software (APIs) and provide a detailed report on the performance comparisons done w.r.t. existing PIPO for a number of varying size testcases.

Authors:  B.Shreeharsha,  Rajesh Khanna, Vikas Arora, Sanjiv Gupta & Abhinavr Rai     

Company: Cadence Design Systems

Title : Digital PCB Design Simulation Solution on the HDL Architecture using INCA verification tools.

     Cadence's  new solution for Digital PCB  Simulation,   in the      SUTTER   release   supports  both   Verilog  and  VHDL  based      simulation using the INCA verification tools.  The main   features      of this  solution  are Mixed Level Simulation, a strong      co-simulation(Verilog & VHDL) support, support for Swift and      Hardware models, Cross probing between ConceptHDL and  Sim Vision,       SDF  Backannotation, testbench  creation and   instance  specific       model  binding.     

     This flow provides seamless  integration  between   schematic      design  and  simulation   using    NC-Verilog  and  NC-VHDL      simulators.

     This paper will discuss the new tools in the flow and their usage.      Evolution from existing PE simulation environment(s) is also covered.       The paper will also bring out the benefits of Native Compiled      Architecture over interpretive simulators and compare the new solution      against LWB on the SCALD  architecture and list the various benefits      of this solution.

Author: Wuudiann (Woody) Ke

Company: Cadence Design Systems

Title: A Design with Testability Framework for a Design Reuse Methodology

Driven by the market forces (i.e. shorter time to market, lower performance/cost ratio, higher quality expectation), companies are rethinking their design, test, and production strategy and methodology, in which design reuse is the center theme for bridging the gap between design productivity and manufacturing capacity. Design reuse and deep-submicron geometries are imposing new challenges on every aspect of product development, including testing complex SoC. To design and test this kind of chips in a reasonable time and cost requires that more work be done prior to chip integration. An integration platform as illustrated in the following figure is a vehicle for creating rapid, low-risk SoC designs within a product application domain. The integration platform should include foundation blocks, which is the fixed part of the intended designs, a library containing prequalified and test-ready virtual components (VC), a baseline scalable architecture (for bus, test, power, clock and timing), and an integration environment for performance evaluation, verification and prototyping. A derivative design methodology should also be established with a set of design and test guidelines.

Author: Bogdan Arsintescu

Company: Cadence Design Systems

Title: Transistor Level Layout Optimization

In the Automated Custom Physical Design (ACPD) flow, the hub for all physical design operations is the Virtuoso (R) XL layout editor[1], which provides advanced interactive and automated capabilities with a significant impact on the productivity of custom design. This paper will describe a new automated utility for device chaining and folding, a unified engine serving the following Virtuoso (R) XL features: 1) device and library generation. 2) connectivity-driven layout generation 3) interactive layout chaining and folding 4) dynamic stack generation for Virtuoso (R) Custom Placer.

This engine uses the connectivity information available in Virtuoso (R) XL to generate optimized layout for devices and blocks especially for MOS device-level placement. MOS devices can be laid out using source and drain diffusion sharing to reduce the area and connectivity density. The auto-abutment feature in Virtuoso (R) XL is used by the chaining and folding engine to create stacked layout for large MOS devices. Moreover, the engine creates an ordered set of abutted devices based on the electrical connectivity. This is generated as a correct-by-construction chain of layout instances for a given sub-circuit. The paper will illustrate device generation using the above features in automated mode as well as in interactive mode.

The chaining and folding engine is also used to generate optimal layout for CMOS leaf cells. The PMOS and NMOS devices are chained in such an order that intra-cell routing is minimized: the device gates in the N and P part are ordered such that the routing can be completed in polysilicon. Moreover, optimal routing for the remaining intra-cell interconnection can be achieved.  To generalize, the connectivity driven layout generation uses the chaining and folding engine to generate optimal layout, preserving the user defined hierarchy.

In the Virtuoso Custom Placer (VCP) solution inside VCP, the chaining and folding engine will be used for dynamic chaining and folding. A series of alternative chaining and folding solutions will be presented to the placer to further increase layout density.

The full paper will include examples of layout generation for leaf cells and for CMOS blocks using the new features. We will also discuss the state-of-the-art algorithmic solutions used to achieve these results.

[1] E.Malavasi et al., Layout Acceleration for Physical     Design, Proc. of Intl. Cadence User Group Conference,     Sep.1998, pp.55-62.

Title: Entering the New Millennium with Web Study Education

Authors: Bonnie Willoughby & Mary Graham

Company: Cadence Design Systems

In this paper we will examine the challenges involved in entering the new millennium using web study techniques.

We will present an overview of different on-line education vehicles. We will show benefits of web-based study. We will talk about techniques such as live training, self-paced CD-ROM based, Web (Internet) based, and live web based training.

Cadence now offers education services solutions in a web-based environment. We will discuss the benefits of this method for our customers. Towards the close of our program, we will present a demonstration of our web-based solution on designing and verifying using Verilog language and the NC Verilog simulator. The future direction and planned enhancements to our current web-based solution will be discussed.

We will summarize by showing our comprehensive education package including our web titles. Our presentation will conclude with Q&A

Author: Enrico Malavasi

Company: Cadence Design Systems

Title: ACPD Custom Floorplanning for Mixed Signal Designs

This paper will present the approach adopted by Cadence to support Custom Floorplanning, specifically for Mixed Signal (M/S) designs, in the context of the Automated Custom Physical Design (ACPD) methodology.

M/S floorplanning has a set of distinct characteristics compared to floorplanning for digital circuits.  These include: á the need for encapsulation of blocks whose structural description   cannot be dealt with by the hierarchy editor á the existence of guard rings, buffers and other special structures   around analog blocks á the need for M/S simulation for analysis á manual editing for most of the analog block, instead of the automated   place & route approaches used for most digital blocks, even of significant   compexity á a very close link between the environment where some of the blocks are   edited (specifically when the ACPD methodology is adopted for block   authoring) and the one where they are assembled.

ACPD Custom Floorplanning includes the following phases: á Constraint handling along the flow and across the hierarchy á Analog and digital block encapsulation as soft blocks, size estimation   and modeling in a M/S environment á Structural and physical hierarchy editing, starting from synthesized   netlist (Verilog, VHDL) or schematic representation of connectivity á Hierarchical block profiling, including area estimation, definition   of constraints on soft pins, pre-routes and power & ground rails. á Hierarchy traversal capability, providing easy transitions between   the block estimation, assembly and authoring environments á Power planning with handling of multiple power supplies á Guard ring generation and optimization á Data preparation and block modeling for place & route tools and sign-off   to automated digital floorplanning (Design Planner)

The paper will contain details about the technology currently provided and planned for the next future by Cadence for M/S floorplanning in the context of the ACPD design methodology.

Author: Larry Bowman

Company: Cadence Design Systems

Title: Project Manager Customization

Project Manager is the next generation navigation tool for the Cadence board design flow. Since Project Manager is HTML based it is possible to create custom HTML flows to launch the Cadence software as well as any other third party applications. This paper will provide examples of the following Project Manager customization techniques.

1. Creating your own personal Project Manager file (.cpm) and using it on existing designs.
2. Creating your own graphics for launching Cadence tools.
3. Making your Company's graphics the default flow for Project Manager.
4. Using Project Manager with Advanced Package Designer.

Authors:Rajeev Narasimhan & Chetan Patil

Company: Cadence Design Systems

Title: BuildGates-Envisia Synthesis Tool. Product validation and testing Methodology

This paper deals with the product validation methodology used in BuildGates-Envisia Synthesis tool internal development stream. The Envisia Synthesis tool is the dependable choice for designers in the million plus gate designs. With an ever increasing customer base and its proven performance, it is critical to ensure that every release shipped out passes a rigorous set of internal performance standards, before it reaches the customers.

This paper provides an in-depth view of the validation and testing methodology, focussing on the environment, the testing flow, tools used, nature and quality of test cases, the testing issues, workarounds and the robustness of the testing environment.

We begin by examining the role of the PV group, outlining some of its key responsibilities and challenges and its significance to the success of the product. Following this, we examine the computing resources that effect efficient product validation and testing cycles and move on to explain the testing environment, the platforms and the operating systems currently supported. A critical part of the testing process is use of the LSF batch resource management system. We discuss how this system is integrated in the product validation process and the benefits it has yielded. Besides, we examine other lesser critical tools such as the Revision Control Sytem used to keep track of multiple file revisions that can be expected in such a mature product.

Following this, we deal with the benchmark tests that form the backbone of the entire product testing across various release cycles. These tests comprise of the test suites from our technology partners, and the ever-increasing multitude of tests from Internal and Field AE's and numerous benchmark tests from our customers. Each release, be it a production release or an internal patch release, completes this extensive array of test cases before it is shipped to the customer. The Ambit PV team ensures that this process is completed as efficiently as possible, thereby greatly reducing the number of showstoppers and last minute bugs in the field, leading to a quality release.

To be able to provide such a wide-coverage, for each and every release, the human-interaction is minimized by the extensive automation of all parts of the validation. This has enabled us to generate releases in short turnaround times without compromising on the quality of the release. We talk about the process automation, the numerous scripts in place and the how this automation has helped us maximize the use of all our computing resources efficiently. We also explain how results generated in real time can help in quickly resolving bug fixes.

The primary objective of the PV team is to allow for consistent, dependable and quality product testing cycles. The paper concludes, by examining improvements to the testing cycle and the how other new product testing cycles can be modeled on the BuildGates testing and validation process.

Title: BER performance of a multi-code W-CDMA system using SPW

Authors: George Efthymoglou, Joseph Boccuzzi (Cadence Design Systems) Saeed Ghasseemzadeh (AT&T Labs)

This paper describes the implementation in SPW of a highly parameterized system designed to compare the performance of multicode and single code implementations of high data rate CDMA systems. Two channel models are used in this simulation study, namely the Vehicular A and Indoor A according to ITU recommendations. The selected rate is 384kbps and the considered processing gains range from 4 to 64. For each processing gain and each channel model the BER with and without power control and with and without antenna diversity are obtained through simulation. The results show that power control combined with antenna diversity significantly reduce the SIR receiver requirement in both fading channel models. Furthermore, QPSK pilot symbols perform better than BPSK pilot. Finally, the BER performance  of the CDMA multicode systems is found to be similar when the ratio of number of codes to spreading factor per code is kept constant, for the two channel models that were simulated.

Author: Chong Hoc Hao & Lily Cong

Company: Cadence Design Systems

Title: Techniques for Fast and Accurate Transistor Level Simulation

In the design of multi-million-transistor system on a chip (SOC) using 0.18 micron technology, one encounters the formidable tasks of verifying the design for correct functionality and meeting the timing specifications.  The standard method using logic simulation is no longer adequate to verify the timing for high performance designs. Due to the pessimism in representing the timing characteristics as cell level delays, not only does one spend more time designing, but the chip also ends up larger and consumes more power.  Furthermore, more advanced and custom design styles are used to achieve high performance and competitiveness, thus requiring one to pay closer attention to the design at the transistor level.  To meet these challenges, one needs more simulations at the detailed transistor levels with parasitics, but finds that the available transistor level simulators inadequate due to slow performance or inaccuracy.  This paper presents some enabling technologies used by Affirma ATS to achieve fast and accurate transistor level simulations of SOC or large complex designs including bipolar and analog circuits. 

These techniques include: mixed MOS timing solver and analog solver, single kernel simulator, automatic circuit partitioning between the MOS timing & the analog solvers, automatic circuit partitioning for faster analog simulation.  Performance improvements due to these techniques will be presented and real examples will be discussed.

Author: Bill Chown

Title: Virtual Test - IC Verification at the test program stage using Verilog.

The verification of IC test programs is a time-consuming and expensive process, made worse by today's VDSM and SoC designs. By applying test programs to the device model through a "Virtual Tester", an accurate Verilog model of the ATE test system, Design-to-Test groups are able to verify design, test and program together before tapeout and fab have committed dollars to silicon. Major users such as Motorola, Sun, AMD, Mitel, etc. have applied this innovative use of Verilog modeling and simulation, and have cut tens of This paper looks at some real axamples from recent projects completed, and presents the application of Verilog-XL and NC, SimWaves and SignalScan to help identify and debug designs earlier in the process, and improve design to test quality and productivity on complex IC and SoC projects.

Author: Fred C. Ford

Company: Cadence Design Systems

Title: Using TCL as a Simulation Control Language

Most simulations use a testbench to set up and exercise the module being designed. This is the way 'it has always been done'. But a testbench is restricted to accessing only the module inputs and outputs. In this paper we will explore a different way of controlling the simulation. An extended TCL shell is linked into the Leapfrog simulator that allows direct read/write access to any net or signal in the design. The result is a reasonably quick and efficient simulation environment. Extensions are also described that permit indirect access to all registers and memories of a design. This TCL interface has been ported to several other simulators including the Cobra, Verilog and Quickturn CoBALT simulators. Additionally, by using the scan chains in the design, the same TCL scripts can actually be used to access the state of the hardware and the tests can be executed on the actual hardware. This work has been done with and for UNISYS Corporation.

Author: Jeffrey Moulton

Company:  IBM

Title: Wrappers to Maintain a CAD Environment

The following key points are made: Setting up new design platforms more efficiently Faster learning curve for a new user (running in hours vs. 1-2 weeks) Easier for CAD group to maintain and upgrade design platform Flexibility of supporting multiple versions of Cadence in parallel Basis for paper Design / CAD experience in the DDA What do I expect to teach?     There is a rapid turn over of designers moving from one project to another. Designers need to make these transitions easily and quickly into new CAD system. I will show a method that I have developed that allows designers to have full access to the system in a very short period of time. I will also show that CAD engineers benefit from this system as well because they can bring new tools up in parallel. What is unique to IBM?     This paper contains no confidential information, only sound software engineering principals that have been proven to work in the DDA CAD environment. Full list of figures Wrappers to Maintain a CAD Environment Meeting Objectives History Sequence of Events Problem Statement Key Issues Potential Solutions Evaluation of Alternatives Recommended Strategy Relative Cost Benefit Analysis

Authors: Robert Shaw and Bradley Jensen

Company: Motorola

Title: Analog Library Automation

The Motorola analog library tools provide numerous advantages compared to previous library development flows. The benefits from this process include reducing the library development cycle time, optimizing yields with higher quality libraries, and limiting mask costs by improving first pass design success. These automation tools increase development throughput, accuracy, and quality by utilizing standardized inputs which are processed using the automation methodology. The tools maximize code reuse, providing consistency across design libraries.

Author: Steve Bird

Company: Hadco

Title: Electrical Performance of Microvias

A microvia can be defined as a small-than-normal via that is formed by some method other than today's mechanical drill process. For example, the hole barrels can be from 3-6 mils in diameter and the pads are typically 10 to 14 mils in diameter. Trace and space features are as small as 3 mils each. These features are rapidly being improved upon, this is the beginning of a new road map for interconnect technology. However, their small size is not the only advantage of microvia technology.

This is a breakthrough not only for