International Cadence Usergroup -

1999 International Cadence User Group Conference

Schedule - Sunday, September 12, 1999

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7:00 - 8:00
Continental Breakfast for Tutorial Students
8:00 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
	Simulation and Modeling	High Speed Design - the ABCs	Automated Custom Physical Design: A Methodology for Increasing Layout Productivity	Data Management - Using TDM / Using Synchronicity

12:00 - 1:00
Lunch(on your own, hotel restaurants available)
1:00 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
	Design Reuse	DFM Fab and Assembly	Hierarchical Block Based Design and Chip Integration Methodology	Cadence Tool Installation and Licensing
	SpectreDirect

6:00 - 9:30
Conference Registration and Social Hour

Schedule - Monday, September 13, 1999

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8:00 - 10:15
Continental Breakfast and Opening Session Opening Keynote: Cadence Technology Development Process Ted Vucurevich - Cadence Chief Architect/Fellow Breakfast Available at 8:00 Opening Remarks and Conference Welcome at 8:45 Keynote at 9:00
10:15 - 10:30
Break
10:30 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
10:30	SIG Opening Remarks and Business	SIG Opening Remarks and Business	SIG Opening Remarks and Business	SIG Opening Remarks and Business
10:45
11:00	Top Issues Review	Top Issues Review	Top Issues Review	Top Issues Review
11:15
11:30
11:45

12:00 - 1:30
Lunch
1:30 - 3:15
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
1:30	Development of Fastrack RF Simulation Capability using Analog Artist	GenCAM Intelligent CAD to CAM Transfer - IPC 2510 Standard	Timing Library Enhancements for Signal Integrity and Reliability	Concurrent Design Environments (Blending NT into an existing UNIX infrastructure)
1:45
2:00	Spectre RF for RF IC Design	PCB Futures: Successful PCB Design for the New Millenium	An Analog Die Size Estimation Tool
2:15				HP EEsof-Cadence RFIC Integrated Design Flow
2:30	BuildGates - Envisia Synthesis Tool, Product Validation and testing methodology		Analog Library Automation
2:45		Helpful UNIX Commands while Designing in Allegro
3:00

3:15 - 3:30
Break
3:30 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
3:30	An Experience Using Inherited Connections in the Custom IC Mixed Signal Design Flow	Extending Allegro, Revisited	Envisia Abstract	Year 2000 Compliance in Stream Files and PIPO
3:45
4:00	Use of Inherited Connections in stdcells library		Parameterized Device Level SKILL Procedures	Product/Release Lifecycle Panel
4:15		Project Manager Customization
4:30	Using the Analog Workbench for IC Design		Stretchable Pcell Functionality in the Virtuoso Layout Accelerator
4:45

5:00 - 5:30
Break
5:30 - 6:00
Meet in Hotel Lobby for transport to offsite event
6:00 - 9:00
Cadence Sponsored Event

Schedule - Tuesday, September 14, 1999

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7:15 - 9:30
Breakfast Guest Speaker: Apollo 13 Commander, Captain James Lovell *Co-sponsored by Cadence & Sun Microsystems* Breakfast available at 7:15 Sponsored by Speaker at 8:00
9:30 - 10:30
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
9:30	Technical Panel	Board Design: Ask the Expert Panel	Technical Panel: DSM Implementation for .18u and below	Ask the Expert: Licensing, NT, and Installation Issues
9:45
10:00
10:15

10:30 - 10:45
Break
10:45 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
10:45	Techniques for Fast and Accurate Transistor Level Simulation	Board Design: Ask the Expert Panel (continued)	Technical Panel: DSM Implementation for .18u and below (continued)	Ask the Expert: Using the Hotline
11:00
11:15			Technical Panel: Plans for Assura Physical Verification
11:30	Enterprise Wide Design Paradigm for Cadence PE Environment
11:45

12:00 - 1:00
Lunch and ICU Board Nominations
1:00 - 1:45
Cadence Technology Directions Keynote Paul McLellan - Cadence Vice President, Strategic Marketing
1:45 - 2:00
Break
2:00 - 3:15
Technology Roadmap Tracks
3:15 - 3:30
Break
3:30 - 4:30
Cadence Topic Panels: Customer Support, Platforms & OS Issues
4:30 - 6:00
Yack and Snack
6:00 - 9:00
Cadence Product Demonstrations

Schedule - Wednesday, September 15, 1999

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8:00 - 9:30
Breakfast Guest Speaker: Pierre Liautaud IBM General Manager - Global Electronics Industry e-business Solutions: The Future of Engineering Starts Here! Breakfast available at 8:00, sponsored by

9:30 - 10:45
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
9:30	A DFII Block Extractor from a Multiple Circuit Description Environment Targeting the SILOS III Simulator	Tandem and Parallism Rules between Allegro and Specctra	Parasitics and RF Design	REPTILE - REPository of Tools, Interfaces, and Other Local Enhancements
9:45
10:00	Performance Improvements in DFII Verilog Import	Advantage Micro-Via	Integrating Inductance modeling in a Cadence Verification Flow	SIG Business, Top 10 Discussion, SIG Chair & Co-Chair Selections
10:15	Non-Monotonicity in Timing Libraries
10:30			DRC Deck Rule Splitter and Builder of a User Specified Rule or Set of Rules

9:30 - 10:45
Break
11:00 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
11:00	BER Performance of a multi-code W-CDMA system using SPW	HDI (IC Packaging)	Process Antenna Effect Verification using Cadence's Dracula of Vampire physical verification tools	Multi-Site Microprocessor Auditing and Data Management Methodology
11:15
11:30	Using TCL as a Simulation Control Language		Hierarchical Methodology, Contract Generation, and Layout Abstraction (blockage modeling)
11:45

12:00 - 1:30
Lunch and ICU Board Selections
1:30 - 3:15
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
1:30	Transaction and Data Driven Verification	Source-Synchronous bus design	ACPD - What is it?	Wrappers to Maintain a CAD Environment
1:45
2:00	Dynamic PLI-Controlled Simulation Enables Concurrent IC Design and Test Development		Transistor Level Layout Optimization
2:15				Performance Enhancement Initiatives in Virtuoso Stream Interface
2:30	RTL Based Object-Oriented Modeling Using NC-Verilog and 'E'	Electical Performance of Microvias	ACPD Custom Floorplanning for Mixed Signal Designs
2:45
3:00

3:15 - 3:30
Break
3:30 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
3:30	A Hierarchical Verification Methodology	SIG Selections	Routing Challenges on a Re-Engineering Product
3:45
4:00	SIG Selections and SIG Top 10 Intake	PCB Design for the Mitigation of EMI	Installation and Setup of the "C" based interface From Virtuoso to IC Craftsman - A User's Perspective	Entering the New Millenium with Web Study Education
4:15
4:30			Automatic Transistor Level Routing with IC Craftsman/Virtuoso using a local-interconnect technology
4:45

5:00 - 5:30
Break
5:30 - 9:00
Vendor Fair Drinks & Hors d'oeuvres will be served

Schedule - Thursday, September 16, 1999

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8:00 - 9:30
Continental Breakfast
9:30 - 10:30
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
9:30	Experience with a Cadence-based Mixed Signal Design Flow	Automated DFx (Design for Excellence) Review	A Custom Datapath Design Methodology	DM Panel Discussion
9:45
10:00	Customizing the Analog Workbench and Concept		A Design with Testability Framework for a Design Reuse Methodology
10:15

10:30 - 10:45
Break
10:45 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
10:45	Concept HDL based Programmable IC Flow	Analog RF	Virtual Test - IC Verification at the test program stage using Verilog	SIG Business: Top Ten Issues
11:00
11:15			SIG Top 10 Issues & SIG Selections
11:30	Digital PCB Design Simulation Solution on the HDL Architecture using INCA Verification Tools	Managing Design and Library Data in the Cadence Intrica Environment
11:45

12:00 - 1:00
Lunch and Speaker Awards
1:00 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
	Tutorials
	Concept HDL Migration	Advanced Specctra Techniques	Getting the Most out of DIVA - An Advanced User Tutorial	Skill Programming - Moving from 4.3.4 to 4.4

Go To: Top / Sunday / Monday / Tuesday / Wednesday Thursday

1999 International Cadence User Group Conference

Schedule - Sunday, September 12, 1999

Conference Registration and Social Hour

Schedule - Monday, September 13, 1999

Cadence Sponsored Event

Schedule - Tuesday, September 14, 1999

Yack and Snack

Schedule - Wednesday, September 15, 1999

Vendor Fair

Schedule - Thursday, September 16, 1999