Simulation and Modeling

Presenters: Rick Munden munden@acuson.com
Steve Durrill sdurrill@cadence.com

Contents: This session covers The details of component modeling, with an emphasis on VHDL. The second half of the session will be a detailed discussion of the Concept HDL interface to simulation. This includes Verilog-XL, Leapfrog, NC-Verilog, NC-VHDL, NC-Sim and a general 3rd party interface.

• The ins and outs of modeling components in VHDL
• Demonstration of Concept HDl simulation solution
• Explanation of the steps in the flow
• How to use wrappers and mapfiles
• Enhancements in the PE14.0 release

Who should attend: Design Engineers interested in FPGA or board level simulation.

DFM Fab and Assembly

Presenter: Helen Lowe, Celestica

Contents: This will be a generic tutorial of the various elements and categories of DFM. Such topics would be generally described around the pro's and con's related to Signal, Fiducial, Testpoint, Soldermask, Solderpaste, etc... analysis. Each part of the tutorial describes why a particular issue is important to manufacturing. The concepts though are 100% generic and can be evaluated manually in the real world or with a CAM tool.

Automated Custom Physical Design: A Methodology for Increasing Layout Productivity

Presenter: Graham Etchells

Contents:

• Connectivity-Driven Layout;
• Relative Object Design;
• Interactive & Automatic Placement;
• Interactive & Automatic Routing.

Data Management - Using TDM / Using Synchronicity

Presenters - Steve Lum/Andrew Beckett/Synchronicity Rep.

This tutorial is designed to provide attendees with an understanding of design management strategies for companies with small design teams to company-wide infrastructures necessary for IP re-use. Product specific implementations will be discussed. The tutorial will also include an overview of the DM product portfolio that is available to Cadence customers.

Design Reuse

Presenter: Steve Durrill sdurrill@cadence.com

Contents: This session covers all the steps required for a complete design reuse methodology. This includes the finer details of the process implemented using Concept HDL, Packager-XL and Allegro.

• Details of the methodology
• Demonstration of the flow
• Explanation of how it was implemented
• Enhancements in the PE14.0 release
• How Reuse of IP reduces time and cost of designs
• How Reuse Enables Top-down approach to PCB Designs
• How Reuse Coordinates multiple site engineering through methodology and infrastructure

Who should attend: Design Engineers interested in enabling reuse of their company's IP.

High Speed Design - The ABC's

Presenter: Todd Westerhoff

Contents:

• Introduction to transmission line theory and how it affects PCB design,
• signal integrity design issues and terminology,
• examination of crosstalk and its effects on PCB design,
• common design techniques for signal integrity
• introduction to CAD tools.

Hierarchical Block Based Design and Chip Integration Methodology

Presenters: Kumar Venkatramani, Han Kim and Tim Decker

This tutorial describes the Cadence Block-Based design methodology. The methodology consists of engineering best practices, t ool flows and specific point tools. The Block-Based Design approach is optimized for a field-of-use that stresses hierarchical block integration of IP components, including new, legacy, and third-party blocks. The processes built into the methodology ar e targeted to reduce risk as much as they are targeted to speed up SOC design. For example, a series of pre-design steps called "front-end acceptance" increases predictability. Cadence has qualified the methodology in its SOC design center, part of Scotl and\rquote s Alba Centre. In the space of Chip Assembly and Integration, this tutorial will also describe among other tools, the use of the tools Design Planner, HyperExtract and IC craftsman.

Cadence Tool Installation and Licensing

Potential Presenters - David Morris/Sashikanth Subramanian

This tutorial is designed to provide attendees with an understanding of the Cadence Stream release model, licensing mechinism, and installation methodologies. Presenters will share recommendations and strategies for administration of Cadence software.

Concept-HDL Migration

Presenter: Steve Durrill sdurrill@cadence.com

Contents: This tutorial covers all information pertinent to the transistion of data from Concept SCALD to Concept HDL.

• Advantages of Moving to Concept HDL
• New Features
• Migration Criteria
• Concept hDL Architecture
• Uprev Methodologies
• Uprev Utility
• Limitations

Who should attend: Anyone interested in the differences between Concept SCALD and Concept HDL.

Spectre-Direct

Presenter: Eric Juergensen juergens@cadence.com

Contents:

• Spectre Direct in IC4.4.3
• Features of Spectre Direct
• Updating spectreS libraries to spectre direct
• Artist Environment changes
• Model File Strategies
• Spectre Direct in Mixed Signal

Who should attend: IC Designers, Modelers, and CAD support.

Advanced Specctra Techniques

Presenter: Dennis Rockwood dlr@cadence.com

Contents:

• Fanout
• Fences
• Copy Commands
• Tax & Cost Strategies
• Rules Strategies
• Tweaking the Placement
• Parallel vs Crosstalk
• Allegro Front End

Getting the Most Out of Diva - An Advanced User Tutorial

Presenter: Steve Soares soares@cadence.com

Contents:

• Advanced Diva Tips,
• New Funcionality and Enhancements,
• Improving Performance (Speed),
• Reducing Memory Requirements,
• Diva and Vampire Compatibility

Skill Programming - Moving from 4.3.4 to 4.4

Presenters - Kris Donate/Dave Kaplan

This tutorial is designed to provide attendees with an understanding of the steps and strategies used for converting databases, rules decks, and Skill code from the 4.3.4 environment to the 4.4 environment. Presenters will share recommendations and strategies for efficient conversion to the 4.4 release.