Title |
Design for Manufacturing/Yield - Redundant Via/Contact Insertion Tool |
Author |
Keith Barkley (presenter) & Thomas Wohlfahrt |
Company |
|
Cadence Tools |
Cadence DFII, Skilll/Diva |
Abstract |
As the geometry's in the newer technologies become smaller and smaller, it becomes increasingly important to build redundancy (vias and contacts) into the design layouts whenever possible. Processing problems during chip manufacturing of inter-level vias and contacts can result is open circuits, especially during the early development of a new technology process. For older, more mature technology processes, having redundant via/contact structures in the design could result in improved chip reliability. Some of the more recent routing tools have the capability of routing with redundant structures as the default via, but this can have detrimental effects on the autoRouted data, macro size increase, increased net length, increased routing run times, etc. A Cadence DFII, Skilll/Diva based series of programs were developed that add redundant via/contact structures to autoRouted or Layout cellViews, custom, semi-custom or fully autoRouted macros. This is done as a post routing operation. The program is parameter based for simple technology updates or migration. It can be run hierarchically or flat and will honor cover macro contracts (blockages passed from above or below) or shadow views (wires passed from above or below). Statistics are reported and a macro database is created for use in making any future runs more efficient. EC capability is also possible. A design rule check can also be run during processing and the program will correct any detected DRC violations. The code was used successfully on the G5/G6 S390 Custom Microprocessors and is being used on current and future processor designs. |
Biography |
Keith Barkley: Advisory Engineer, Design Tools/Methodology Developement |
Title |
|
Author |
Donna J Ducharme |
Company |
Texas Instruments |
Cadence Tools |
Virtuoso 4.4.3, Virtuoso 4.3.4 |
Abstract |
Cross Probing utilities have long been considered a verification tool. Presented will be some of the many reasons why cross probing should be available on every desk top involved in the design cycle and how we implemented it into our environment. The cross prober being used in this example is DIVAFWD, a Viewlogic product. Presented will be a custom Perl utility which provides a simple to use solution to every job function involved in the design process. Development of standardized database storage made developing this routine simple. Some of the difficulties were the different media types and how the DFII 4.3.4 or DFII 4.4.3 of Cadence react to unix symbolic links. The following considerations had to be taken into account when writing this utility: Minimizing write access to the database Minimizing training involved with rolling this product out to a non-Cadence or unix savy user community Minimizing waste of disk spaceThe final results are the Unix directory tree that is setup by the Perl utility for DFII 4.3.4 or for DFII 4.4.3. The amount of hand tracing and plotting has diminished with very little training and high usage of this process. The above were concepts which were implemented at TI(Unitrode), however these concepts can be easily implemented in a front to back solution. |
Biography |
Usage of Cadence tools for the past 16 years. For the past 5 years she has worked in support of Cadence tools. Key responsibilities are writing skill pcells, productivity enhancement utilities, defining layout methodology and user training. ICU Board member. |
Title |
|
Author |
Robert Dwyer and Adam Jatkowski |
Company |
IBM |
Cadence Tools |
SKILL Programming, Virtuoso, Preview, Hierarchical Design, Soft Pin Optimizer |
Abstract |
One of the more difficult tasks in hierarchical integrated circuit design is determining optimal locations for pins (that establish where interconnection between levels of hierarchy occur). Since none of the available tools provided exactly the solution and ease of use the team desired, we decided to write our own. Using Cadence SKILL, a menu driven, user-customizable solution was developed. The pin optimizer attempts to find the solution that minimizes the total orthogonal distance between all pins, aligns neighboring pins when possible, and balances the length of the bits in a bus. The tool can easily be adapted to work with any technology, and gives the user enough granularity of control while still being very easy to use. No database translation is required since the design is read, analyzed, and modified within the DFII Framework. The algorithm developed, techniques used, and difficulties encountered while implementing this solution will be discussed. |
Biography |
Mr. Jatkwoski is a Staff Engineer in the S/390 Hardware Development Laboratory. He received his B.S. in Computer Engineering from The Pennsylvania State University in 1997, and has worked for IBM since 1997. Mr. Dwyer was a Staff Engineer in the S/390 Hardware Development Laboratory in Poughkeepsie, New York. He received his B.S.E.E. from Northern Arizona University in 1996, and joined IBM in 1997. He currently is employed by Sequence Design in Acton, Massachusetts. Both authors have contributed towards the physical design of S/390 CMOS microprocessors, and have been involved in developing methodology-specific design automation solutions. |
Title |
Pegasus: making dfII application fly over the Genesis infrastructure |
Author |
Lamant, Gilles |
Company |
Cadence Design Systems Inc. |
Cadence Tools |
dfII / CDBA / Genesis / Virtuoso |
Abstract |
As design size and complexity grow, the problem of storing large databases and moving them between tools in a flow is more difficult to solve. In order to improve our Synthesis Place & Route (SP&R) and DiAblo (CMS) solutions, it becomes necessary to move the tools in these flows to a common infrastructure. The Pegasus project is the first step in unifying different tool families onto a single infrastructure. By unifying the design data repository, the tools share the same data, and designers will no longer need to translate to a secondary format in order to go to the next step in their design flow. This paper will provide an overview of the "Pegasus" project, and will initiate the presentation of some of the new database objects and concepts used in this infrastructure. |
Biography |
Gilles Lamant received his Engineering degree from E.S.I.E.E (Ecole Superieure d'Ingenieurs en Electronique et Electronique) in Paris, France in 1991. Since 1993, he has been working with Cadence Design Systems, focusing on working directly with customers and improving their designs flows. In that context, and since 1994, he has focused on the mixed-signal flows, covering all aspects from the front-end to the back end. He is currently a Senior Project Manager with the Cadence Service organization, and involved with the R&D organization for the definition of the future infrastructure. He is based in Tokyo, Japan. |
Title |
|
Author |
Mar Hershenson |
Company |
Barcelona Design |
Cadence Tools |
There is currently no equivalent tool available from Cadence. The product of Barcelona's synthesis can be used to drive Cadence's analog simulation and layout tools. |
Abstract |
While there has been an accepted digital design methodology for years, analog designers have not had the luxury of such advanced tools. We will present a new analog flow - a method for the design and sizing analog circuits, that feeds the established Cadence back-end tools. Barcelona optimizes circuit design very accurately and quickly, generating a sized netlist to take to Spectre and a floorplan for Virtuoso. With this new flow designers can within seconds, see how increasing one spec, say power, impacts layout. This ability to automate the design of small blocks will enable designers to do more system-level tradeoffs in their design of subsystems like ADCs or PLLs. |
Biography |
Mar Hershenson graduated with honors with a BSEE degree from the Universidad Pontificia de Comillas in Madrid, and MS and PhD degrees in electrical engineering from Stanford University. Her research, with Professor Stephen Boyd and Professor Tom Lee, was on a radically new method for automating analog circuit design using convex optimization. Her research work is the basis of Barcelona's technology. Her experiences at Stanford range from teaching analog circuit design courses to working on the design team for a single-chip CMOS GPS receiver. Hershenson has also worked as an analog circuit designer at Linear Technology Corporation and Apple Computer. |
Title |
Bitstacking With Only A Composer Schematic Editor License |
Author |
Tony Laundrie |
Company |
SGI |
Cadence Tools |
Composer schematic editor, Virtuoso layout editor, v4.4.x |
Abstract |
The circuit designers for a recent Silicon Graphics project wanted to manually specify the placement of standard cells. Their schematics were created in Cadence using a library of IBM standard cell symbols. The target place-and-route tool was IBM's Chipbench/Chipedit, which we had in house. In the past, hand-drawn sketches or Framemaker drawings were given to a Chipbench expert for cell placement. We wanted to give the schematic designers a slightly more powerful bitstacking tool, but without forcing them to leave the Cadence framework, and without spending money on additional licenses or new tools. The project had plenty of Cadence schematic editor licenses, but Cadence layout editor and IBM Chipbench licenses were scarce. This paper describes how we used a perl script to convert IBM's VIM/PHYSICAL format into Cadence abstract views, then how we wrote Skill code to initialize a "floorplan" view, display flight lines, and write the final placement in IBM's Chipbench format. This allowed our circuit designers to arrange standard cell abstract views within a floorplan drawing using only a Cadence schematic editor license. |
Biography |
Tony Laundrie has a Masters Degree in Electrical Engineering from the University of Wisconsin at Madison, and presently works for Silicon Graphics in Chippewa Falls, Wisconsin. Job duties have ranged from CAD support, logic design, computer architecture, and custom VLSI design. |
Title |
|
Author |
Paul G. Mason |
Company |
Cadence |
Cadence Tools |
VirtuosoXL, Virtuoso Custom Placer, Constraint Manager |
Abstract |
This paper will cover the variuos use models for the Virtuoso Custom Placer device level mos, standard cell, mixed mode. Setup for running the placer, tips on improving the placer results. Show some example outputs from the tool. |
Biography |
graduate of Wentworth Institute ASEE 1979 working on BS/MSEE Kennedy Western University 18 years design support engineer at Analog Devices 3 yrs at Cadence Design Systems currently a product validation design engineer |
Title |
|
Author |
Paul G. Mason |
Company |
|
Cadence Tools |
Virtuoso XL, Constraint manager, composer, VCR |
Abstract |
The Constraint manager allows the various design considerations to be captured through out the development process. This saves time relaying the important information from person to person. It enables both interactive and automated tools to drive the design signal integrity and placement. This also saves ramp up time for ECO's since the critical information will be archived with the database. |
Biography |
graduate of Wentworth Institute 1979 ASEE currently working on BS/MSEE at Kennedy Western University eighteen years experience working at Analog Devices converters, amplifiers, linear circuits, mixed signal designs. three years working at Cadence currently as a Design Engineer for Product Validation |
Title |
Formal Methods in Functional Verification of Circuits: An Overview |
Author |
Scott Meeth |
Company |
Sun Microsystems, Inc. |
Cadence Tools |
Affirma Equivalence Checker, Affirma FormalCheck model checker |
Abstract |
Formal methods give hope to those struggling with the task of verifying the functionality of increasingly complex circuits. Formal hardware verification can provide better coverage than conventional methods, with a comparable amount of effort. This paper gives an introduction to, and an overview of, some formal methods as applied to the functional verification of sequential circuits. The paper discusses the formal FSM model that two formal methods (Equivalence Checking and Model Checking) employ, and compares these methods to conventional simulation. For each of three formal methods (Equivalence Checking, Model Checking and Theorem Proving), the paper discusses motivation, how the method works, how to use the method, and some examples of tools (both industrial and academic). Two more formal methods are briefly discussed (Symbolic Trajectory Evaluation and symbolic simulation). |
Biography |
Speaker has worked in ASIC verification at Sun for 4 years. His last project there was to verify the USB Host Controller in the integrated I/O ASIC for Sun's next-generation workgroup server platform. Speaker holds MS Mathematics and MS Computer Science from University of Illinois at Urbana-Champaign. |
Title |
|
Author |
Thomas Moerth Presenter Navraj Nandra |
Company |
Austria Mikro Systeme Int. AG - Austria |
Cadence Tools |
SpectreDirect, IC 4.4.3, ROD pcells, |
Abstract |
Austria Mikro Systeme Int. AG offers a high performance 0.8um SiGe BiCMOS process to its customers. The presentation will give a short overview of the process itself, and will then describe how the design kit for this technology is implemented using the Cadence design environment. The design kit makes use of most of the new IC 4.4.3 features including SpectreDirect simulation, the Corner tool, ROD pcells, and inherited connections. Austria Mikro Systeme Int. AG has also implemented a "Safe Operating Area Check" for this technology. |
Biography |
Title |
UTMC Gate Array Cell Generator using Cadence Relative Object Design> |
Author |
Stacia Patton |
Company |
UTMC Microelectronic Systems |
Cadence Tools |
DFII, SKILL, Relative Object Design |
Abstract |
A cell generator for UTMC's library of core logic gate array cells is implemented using Cadence's Relative Object Design (ROD) software. The ROD functions use design rules to create and align ROD objects. Design rules can be specified for different foundries and technologies or can be altered to specific design needs. ROD user-defined "handles" are created to facilitate internal routing and to accommodate different UTMC architectures. Hierarchy is used to minimize the ROD code, and a Cadence Skill Makefile generates the entire library automatically. |
Biography |
Stacia Patton received her B.S. degree in electrical engineering from the University of Colorado, Colorado Springs in 1990. She has been employed as a design engineer at UTMC Microelectornic Systems in Colorado Spings since 1994. Peter Pohlenz received his M.S. degree in computer science from the University of Illinois at Urbana-Champaign in 1987. He has been employed as a CAD engineer at UTMC Microelectronic Systems in Colorado Springs since 1988. |
Title |
|
Author |
Julia Perez |
Company |
Motorola SPS |
Cadence Tools |
Virtouso & ROD |
Abstract |
This paper presents an assessment of the ROD capabilities as they relate to complex analog bicmos requirements for development of Parameterized Cells. The complexity requirements presented have been encountered in 15 of the 17 analog technologies developed at Motorola. The functionality, flexibility, ease of support, ease of integration with the Motorola custom functions and speed of compilation were key considerations. The task of crafting a pcell has improved using ROD but further improvement in functionality and speed is desirable. ROD does not meet the pcell development capabilities that Motorola already has in place. Motorola has considered needs in relative shape relationships for polygons with arch and diagonal corners, via and contact capability, shape connectors,calculations required in coding such as repeated shapes spacing, relative object relationship needs and ease of coding pcells. Part of the ease in coding pcells is a simplification of parameters in how a relative shape is coded. This paper shows how the ROD functions can be used in an integrated development environment with other custom functions and makes suggestions as to extensions to the ROD functions which would significantly enhance its appeal. |
Biography |
Julia Perez has been with Motorola for over 5 years. Julia has worked in the fab, rf design, and CAD development. She has a BSEE in electrical engineering and is currently pursuing her masters. |
Title |
|
Author |
Sue Strang |
Company |
IBM Corp. |
Cadence Tools |
Assura, Analog Artist, SpectreRF |
Abstract |
As frequencies get higher and wavelengths are approaching design dimensions, transmission line analysis is becoming a more integral part of design verification for integrated circuits. This paper discusses two methods to analyze transmission line effects on IC's. Simulation of the effects of transmission lines may be analyzed through distributed segments of a parasitic network through Cadence's Assura verification program. A patented methodology is employed to segment the line for analysis. Another approach is to model these effects using Cadence's Transmission Line Generator for a wiring instance to create a lumped-circuit model. A cross section view of the transmission line can be displayed. This custom lumped-model single-ended or co-planar transmission line can be verified within Assura using a black box method to exclude parasitics and check in line parameters. |
Biography |
Sue Strang is employeed by IBM Corp. in Essex Junction, VT. She is responsible for design kit and model development for the IBM SiGe technologies. |
Title |
|
Author |
Ron Rohrer |
Company |
Neolinear |
Cadence Tools |
Neolinear's circuit and physical synthesis products complement and automate the Cadence analog design solution dramatically reducing time-to-GDSII for analog/mixed signal SOC designs. |
Abstract |
Neolinear offers an analog cell design flow that integrates with the Cadence environment. NeoCircuit for analog synthesis uses any customer simulation environment (e.g. Spectre) to size/bias Composer schematics. These sized schematics are read into NeoCell for automatic placement and routing of analog cells (e.g. utilizing Cadence pcells). Upon Diva/Assura verification, the analog cell is read into Virtuoso for block level design. This solution is constraint-driven. By capturing the designer's intent, IP is created enabling rapid technology migration and foundry re-targeting. |
Biography |
In addition to an academic career at leading universities including UC-Berkeley and Carnegie Mellon, Dr. Ron Rohrer started his industrial career at Fairchild Semiconductor in the 1960s, and has since served as technical consultant and advisor to many leading EDA and electronics companies. In the early 60's, Rohrer began using optimization techniques for the design of integrated circuits (ICs), and in 1989 he was inducted into the National Academy of Engineering for his contributions to circuit simulation that have enabled deep submicron IC design. Among his many awards is the 1996 NEC Computer and Communication Prize, a worldwide honor for pioneering contributions in electronics. An entrepreneur, Rohrer is currently chairman of Neolinear and previously founded Performance Signal Integrity, Inc. which was acquired by Integrated Silicon Systems and later merged with ArcSys to form Avant! Corporation. |
Title |
HFC ToolBox: A number of utilities for the a Full Custom Hierarchical Design |
Author |
Salvatore Santapa' |
Company |
STMicroelectronics |
Cadence Tools |
Virtuoso XL - ICC |
Abstract |
This paper will present the HFC (Hierarchical Full Custom) ToolBox user interface that provides a solution for the top-down hierarchical flow in mixed signal physical design. This ToolBox is a SKILL user interface that aids the designer in the various steps of the flow. This interface completes the Cadence ACPD methodology in the following areas: - Hierarchical floorplanning - Power & Ground planning - Pins optimization - ICC constraints files generation - Arcadia parasitics extractor integration - Pre-Layout netlist backannotation. |
Biography |
9 years experience in the IC designing. Today I work in Central R&D - Unicad Support Group Current job: Senior Applications Engineer |
Title |
|
Author |
Laurent Thenie |
Company |
Cadence Design Systems |
Cadence Tools |
Virtuoso, Assura Physical Verification, Dracula, Diva, Vampire |
Abstract |
As silicon industry enters the "Very Deep submicron era ( < 0.25 micron )", manufacturers face a new challenge. IC features get now smaller than the wavelength of light used by optical lithography equipment. Optical aberrations inherent to this situation occur during optical exposure of the wafers. The solution in fabrication would be to decrease the wavelength of steppers which is today most commonly at 248nm. This will not happen in the near future and other solutions had to be found. Fortunately, emerging software technology called Optical Technology Correction has been developed by our partner Numerical Technology and integrated into Cadence Assura Physical Verification. Many people already implemented simple OPC rules in their rule files, either using Dracula, Diva or Vampire. We will describe the methodology that we can put in place to very quickly implement these opc rules using Assura, and improve the overall performance (cpu, memory, disk). Secondly, we will see how we can get more accurate and reliable opc correction by using all the functionality of the tool. Two levels of calibration (lithography and process) can be performed in order to let the tool decide of the best correction to be applied based on internal simulation results. Finally, we will present the new "aerial image" capability which has been integrated into Virtuoso. Layout engineers can view on their screen the layout as it will be printed on the wafer based on lithography simulation. We will see on practical examples that the implementation of this new technology can be achieved easily and successfully by using Assura. |
Biography |
- Engineer from "Ecole Nationale Superieure de Physique" Marseille,France - Master of Science in Computing Science "Ecole des Mines" Ales, France - Has been working in physical verification, mask preparation in foundries and EDA companies since 1981 : MATRA-HARRIS, EXEL MICROELECTRONICS, ATMEL-ES2, COMPASS DESIGN AUTOMATION, CADENCE DESIGN SYS |
Title |
|
Author |
Sze Tom |
Company |
Motorola Inc. |
Cadence Tools |
Virtuoso layout |
Abstract |
A common use of ROD (Relative Object Design) has been to create procedural pCell of transistors. This paper describes an application of ROD to create complete layouts. ROD has an added capability over the standard shape create functions in that it can manage shape relationships to each other. This additional level of abstraction has made it practical to use ROD Skill functions to implement layout synthesis. Without it, the mathematical computation overhead would dominate the task. The ROD construct has been applied to create finished layouts of simple gate functions such as inverters, nands, and nors. These functions are ideal candidates for layout automation. Their transistor topology are very well understood. They also have very regular, repeating structures, and are fixed in size in one dimension. The code was developed in a modular manner. A Skill procedure was written to create a device. Separate procedures were written for a 1-finger and 2-finger gate that calls the device procedure. Another procedure was written to create a gate layout of any number of fingers by calling the 2-finger and 1-finger procedures multiple times. A gate with even number of fingers calls the 2-finger procedure n/2 times. A gate with an odd number of fingers calls the 2-finger procedure (n-1)/2 times, and the 1-fingered procedure once. This hierarchical approach to creating the gate layout avoided the need to route the layout. Each finger procedure already contains the necessary connections. The finished layout is flat. |
Biography |
Sze currently works in Motorola's PowerPC tools and methodology group in Austin, TX. He has a Bachelor's degree in Electrical Engineering from Polytechnic Institute of NY. |
Title |
|
Author |
Mark Townsend |
Company |
CPClare Corp |
Cadence Tools |
Vituoso |
Abstract |
A DMOS is an array type device, looks something like a waffle. We already had cells to build the array, but needed a way to quickly build different sized arrays according to the Ron ( the on resistance) that the engineer wanted. This paper describes the code that was used to code the Pcell. How the array size is chosen and coded? How ROD is used to align the cells once they were placed. Being able to quickly get several DMOS devices laid out quickly enables the layout Person to give feedback to the designer as to which specific size will work in the layout. |
Biography |
I have been doing full custom layout for 17 years. The last 4 years at CPClare. We design high voltage analog products for telephone circuits. One of the devices that we have in most of our products is a high voltage DMOS. These are large array type devices that have to take up to 360 volts.. My responsibilities have been the include the layout of product, procedures, verification including writing runsets, mask works and writing any code that will increase productivity. In other words I do the entire layout job. |
Title |
|
Author |
Andreas Wassatsch |
Company |
University of Rostock, Dept. EE&IT |
Cadence Tools |
Synergy/(Envisia Ambit), Gate/Silicon Ensemble |
Abstract |
Dynamic circuit implementation style is a common technique for high performance applications like microprocessor or DSP design. Due to the different characteristics of the dynamic cells compared with static CMOS circuits we need adapted synthesis methods. Unfortunately, there is no standard CAD support for dynamic CMOS logic until now so the design of these high speed circuits has to be done mainly manually. In this paper we present a solution and the necessary toolset to close this design gap by integrating dynamic circuit technology into the standard CMOS design flow. We will show that the chosen Java based realisation of the necessary toolset can fulfill the requirements of an industrial circuit development process with the advantage of a platform independent implementation. Due to the different requirements of dynamic circuit cells we will give some indications to achieve good results in terms of speed and area in the resulting dynamic circuit design. First results from evaluating the proposed design flow on real design projects are also available and will demonstrate the feasibility of our solution. |
Biography |
Andreas Wassatsch studied electro-technology at the University of Rostock. Since 1997 he is as scientific worker at the institute for applied microelectronics and data processing of the university of Rostock. He is there active in the area of the development of hardware Design-flows for high-speed logic and of appropriate architectures for digital signal processing. |
