Title |
|
Author |
Steve DiBartolomeo |
Company |
Artwork Conversion Software, Inc. |
Cadence Tools |
Cadence APD (Advanced Package Designer) |
Abstract |
Cadence APD (Advanced Package Designer)|45 Minutes|Infocus||The packaging of complex integrated circuits can be made simpler and more effective if the IC designer and the package designer work together prior to final device tapeout. This paper describes a WEB based server application that enables IC designers to preview how their die will appear in the package and to move pad/nets around to avoid potential problems when routing the package. Because this is a 100% server based tool, the IC designer does not need any software other than a browser and PDF plug-in. |
Biography |
Steve DiBartolomeo is president of Artwork Conversion Software and has been involved in microelectronic design since the late 1970's. He graduated with a BS/MS in Electrical Engineering from UCLA in 1978. Currently he is involved in developing automation software for IC packaging including tools for automatic wirebonding, DRC, and integrating IC layout with package design. |
Title |
Linking Cadence PCB Tools to a Product-Data Management System |
Author |
Leonid Lokchine |
Company |
Schlumberger SRPC |
Cadence Tools |
|
Abstract |
Over time, CERN* experiments have grown from somewhat larger than table top to industrial-scale undertakings. Next-generation experiments, due to operate by the year 2005, count millions of detector-electronics channels. Some 1800 people from 150 institutes from around the world work on the construction of a single experiment. These numbers illustrate the necessity to use a product-data management system (in our terms: EDMS for engineering-data management system) throughout the design, construction, and operation (over some 20 years) phases of such large projects. This presentation will describe how Cadence PCB tools are linked to the EDMS in use at CERN. It will start with a brief introduction on EDMS, design flow issues, requirements, and then discuss the available alternatives. Next, it will describe how a commercial product has been selected, customised, and introduced. Finally, the experience gained from the first applications will be reported. |
Biography |
Title |
|
Author |
Frank Grano |
Company |
SCI Systems |
Cadence Tools |
Cadence Allergo |
Abstract |
Automating the DFM Process The DFM process has typicaly been a manual process using the expertise of the manufacturing engineering staff. They have to manually sort through all of the documentation available at a given time and use the experience gained in previous assembly operations to decide the manufacturability of a given design. A better method would be to collect this knowledge base and use then computers with the appropriate software to automate this process. In addition to having a process that is automated it could now be done at the design level before any documentation is available to the manufacturing engineers. The appropriate changes can then be made before a product is released into the prototyope process. This paper will examine the installation of the Valor Trilogy software and the impact it has had on the design process and the release of a product into the manufacturing process. It will look at the installation and use of this product and how it has been integrated into the design process. |
Biography |
Frank Grano is a Principal Process Engineer at SCI systems currently working with the design group and is responsible for the introduction of new products into manufacturing. He has worked in electronics manufacturing since 1979 with several large OEM's and in the EMS industry for the last 8 years engaged in new process development. |
Title |
Physical Design Checking and Simulation Model Verification with Specctraquest. |
Author |
Brad Herrman |
Company |
IBM |
Cadence Tools |
Specctraquest |
Abstract |
Physical design can't often be finished in a timely manner and still meet boundary conditions stipulated by component suppliers. Boundary conditions stipulated by a component supplier can be captured in Sigxp topologies. The topologies can be supplied by component suppliers or developed locally from information supplied by the component supplier. The topologies are imported into the Allegro database and applied to related nets. As the layout process proceeds, the layout person is made aware of situations that are outside the design space with visual symbols like DRC bowties or with the timing spreadsheet or with detail reports like the Specctra's length and delay report. Concurrent with the layout process, simulation models that were taken on faith can be qualified. Models can be tested to worst case boundary conditions that have been stored in Sigxp topologies. These Sigxp topologies can be used to define test boards that CCT can route quickly. Exercising models in extracted circuits from layouts with known boundary conditions can reveal the quality of the model. When layout process can't achieve compliance, Specctraquest can be use to analyze situations outside the limits stipulated by component suppliers. Risk analysis can be done with simulation that use locally qualified models. |
Biography |
Title |
Comparison of SI Simulation Results and Lab Measurements: A Forensic Case Study |
Author |
Kim Helliwell |
Company |
Acuson Corporation |
Cadence Tools |
SPECCTRAQuest, SigNoise |
Abstract |
A redesign of one of Acuson's boards required a signal integrity analysis of the clock lines. This analysis was undertaken using Specctraquest/Signoise. Lab results from these clock lines were available, making direct comparisons of the simulated and measured results possible. For many of the clock lines, the simulated and measured results were reasonably close. A few of the simulations showed inflections on the rising and falling edges that were not present in the measured results, or were only present as a slight shelf. It was conjectured that the kinks were actually present, but were missed in the lab measurements due to bandwidth limiting. Matlab programs were written to perform one and two-pole bandwidth limiting of the simulated waveforms, and it was found that a two-pole filter with poles at 400 MHz and 750 MHz made the simulated results match very closely with the measured results. From this investigation, it was concluded that care is needed in interpreting simulated results when the available lab equipment is bandwidth limited compared to the risetimes of modern components. |
Biography |
Kim Helliwell began his career in wafer fab process development, but quickly found an interest in software tool development and support. He joined Analog Design Tools in 1984 and helped develop the circuit simulators for the Analog Workbench. He continued this work at Valid Logic Systems, Inc. and then joined Cadence as the manager of the Spectre core development group. He currently works at Acuson supporting analog circuit simulation and signal integrity tools for the design community there. |
Title |
IBIS documentation, library management and user support at 3Com Carrier R&D |
Author |
Roy Leventhal |
Company |
3Com |
Cadence Tools |
SpecctraQuest & SigXP |
Abstract |
3Com is ISO9000 certified and our IBIS modeling process has been documented. The how, what, and why of describing, obtaining, using, understanding and managing IBIS models for our PCB board Signal Integrity design flow will be presented. As well, how to avoid the pitfalls of the ISO 9000 certification process will be presented. |
Biography |
Roy Leventhal works at 3Com in Mt. Prospect as a Sr. Signal Integrity Engineer. He earned his BSEE & MSEE at Illinois Institute of Technology, the latter in 1966. More recently he was in the PhD EE program at the University of Wisconsin - Milwaukee before that was interrupted by career moves. His main area of study was RF and microwave. Previous experience includes RF circuit design; semiconductor physics and discrete transistor applications and product development; component reliability engineering, and; component library management. Most recently he has been doing analog circuit and mixed systems simulation, and; high speed digital (SpecctraQuest) circuit simulation and signal integrity training support for product design engineers. |
Title |
|
Author |
Leonid Lokchine |
Company |
Schlumberger SRPC |
Cadence Tools |
|
Abstract |
This presentation shows the implementation of an optimised PCB Design flow in Schlumberger SRPC, which is one of the three Wireline & Testing Product Centres of Schlumberger. The project has been done in co-operation with Cadence Consulting Services. Cadence brought its expertise in design process audit, PCB design and manufacturing. The objective was to introduce a powerful PCB design tool running on Windows NT, simplifying the current PCB design flow, while preserving the previous designs. With the help of Cadence Consulting Services, Schlumberger achieved this challenge. Cadence contributed in understanding the actual process and methodologies in usage at SRPC, and transformed it into a new flow. This project was done in four main phases: specifications of the new environment, migration of PCB libraries and designs from Scicards, development of complementary procedures to suit SRPC's needs, and end-users ramp up. This project has been an opportunity to clean-up the 15 year old PCB library, removing old symbols and standardising remaining ones. The project has been successfully achieved in a challenging timing. This integrated commercial environment brings for SRPC a reduction of global infrastructure costs in a medium term, and an opening to external sub-contractors. |
Biography |
Title |
|
Author |
Dave Kehmeier |
Company |
|
Cadence Tools |
|
Abstract |
What do you need to do to integrate Allegro with your mechanical design application? This paper begins with a quick overview of the Intermediate Data Format (IDF), the de facto industry standard for MCAD/ECAD data exchange. Then it discusses the key process, library, and data exchange issues customers face in integrating Allegro with mechanical design. Integration concepts are illustrated with case studies of integration processes at Sun Microsystems, Cisco Systems, and other companies. |
Biography |
Dave Kehmeier is the founder of Intermedius Design Integration, providing consulting services to help companies develop and implement effective integration between Mechanical Design and PCB Layout, using the IDF. Dave is responsible for the ongoing development and support of the IDF. Prior to Intermedius, Dave spent nearly 9 years with Mentor Graphics in various management, marketing, and consulting positions, all related to the design, implementation, and integration of PCA design and CAD/CAM/CAE systems. He has over 15 years' experience in the CAD/CAM/CAE industry. |
Title |
|
Author |
Kate Mayer |
Company |
Mayer Design Services |
Cadence Tools |
SPECCTRA |
Abstract |
This presentation will share the author's strategies on how to best use the Specctra autorouter on the most difficult designs. These tips, techniques, and tricks are based on understanding how Specctra looks at routing problems; and the determining the necessary rules, design parameters, and strategies to route your designs. The guiding philosophy is to encourage "teaming talented designers with a powerful design tool." and follow the philosophy that route failure always has a reason. The effective SPECCTRA user employs the SPECCTRA design tool to isolate and overcome the reasons for route failure by re-routing with influences. Proper use of SPECCTRA cuts design time and minimizes the tedious aspects of printed circuit design. |
Biography |
Kate Mayer has been continually involved with PCB Design since 1971. Known for her dislike of autorouters during the 1980's, she changed her mind after using the SPECCTRA autorouter in 1992. It quickly became her tool of choice and she developed design techniques tailored to harness the power of SPECCTRA. She calls herself a "lazy" designer, content to be the "director" of autorouting, while SPECCTRA performs all the tedious, time-consuming design tasks. Kate is currently teaching and doing design work for her company, Mayer Design Services. |
Title |
A Review of PCB Manufacturing Formats and what they mean to you |
Author |
Joe Morrison |
Company |
ADIVA Software |
Cadence Tools |
Allegro, APD, Specctra |
Abstract |
Over the course of history, there have been many different methods and schemes used to build PCBs from design data. In the days of Bishop tape, photographic contact prints provided this information. Since the invention of Computer Aided Design Systems, there has been a need to provide electronic data to manufacturing. This presentation will discuss many of these data formats, and identify the strengths and weaknesses of each. In addition, the common formats used today will be compared with each other and new, emerging standards. |
Biography |
Joe Morrison is the current ICU Chairman, and has been a member of the ICU board for four years. In his spare time, he is the Director of Technology for ADIVA Software, which creates Manufacturing Simulation software for PCB analysis. Joe has been in the PCB Cad business for 17 years, concentrating on the areas of Routing, Manufacturing Interface, and Tool Integration. |
Title |
|
Author |
Carl Musetti |
Company |
General Instruments |
Cadence Tools |
Allegro DRC |
Abstract |
The Allegro DRC system can be a powerful tool in aiding you to design it right the first time and throughout the life of the product. This paper will show the benefits of designing without DRC markers as well as point out the disadvantages of releasing your design to manufacturing with DRC markers present in the database. The paper will also discuss the disadvantages of not properly modeling the DRC constraints that are indicative of the electrical and mechanical rules of the design. |
Biography |
Carl Musetti is the PCB SIG chair for the ICU. Carl has been in the EDA industry for 19 years now. Carl has worked for several electronics companies such as ASI, General Instrument, Motorola, and has even worked for Cadence. During his 19 years in the CAD industry he has designed boards, administered CAD systems, written CAD utility programs, and managed a Service Bureau. |
Title |
|
Author |
Dave Seymour |
Company |
Tekelec |
Cadence Tools |
|
Abstract |
Allegro has one of the most complete third party netlist interfaces available. Getting the most out of this interface leads to better design results. This paper Will specifically discuss the common pit falls of device files, the use of constraints and properties with an emphasis on Viewlogic. |
Biography |
David Seymour is a PCB SIG co-chair for the ICU. David has been a PCB Designer in the Electronics industry for over 17 years. He has worked for several electronics companies such as Borg-Warner, Wolfdata, Atex, and Tekelec. During this time he has designed many different styles of PCBoards including High-Speed, Micro Via, Compact-PCI, and Micro-BGA. |
