Title |
Wizard for configuring simulation interfaces (PLI, VPI, Verimix, Swift, etc.) |
Author |
Sanjeev Aggarwal |
Company |
Cadence Design Systems (India) Pvt Ltd |
Cadence Tools |
Verilog-XL and NC-Verilog |
Abstract |
PLI Wizard utility was released for the first time in January 2000 and offers tremendous ease of use to thousands of designers using Verilog-XL and NC-Verilog. It has been very positively received by our AE community and now needs platforms for being showcased to the prospective users. The PLI Wizard utility simplifies the procedure of building PLI applications for integration with the Verilog-XL simulator and the Affirma NC Verilog simulator. The PLI Wizard utility interactively accepts inputs from the user through a Graphical User Interface(GUI), analyzes these inputs and translates them to the required C files, the makefiles and the command file. These files are subsequently used by the PLI Wizard utility to build the simulator and the PLI shared libraries. Apart from linking PLI applications, the PLI Wizard utility also facilitates linking of other components to the simulator. Maximum benefit offerred is through facilities like:
Overall, it is expected to offer ease of use to the designer community by allowing them to specify "what" interfaces they want to link instead of them having to say "how" to link in. |
Biography |
Sanjeev Aggarwal Bachelor of Technology in Electronics & Communication Engg. from IT-BHU, India (year 1993). Have been with Cadence since 1994. Worked on simulation/synthesis library modelling and TLF timing libraries. For the last ~3 years, part of the Verilog-XL R&D team in the capacities of an individual contributer and currently as the engineering manager. Pratik Mahajan Bachelor of Technology in Computer Science (year 1996). Have been part of the Verilog-XL R&D team since late 1998 and has been working on simulation core and interface technologies. |
Title |
|
Author |
Mario Aranha and Michael Burt |
Company |
Agilent Technologies |
Cadence Tools |
DFII version 4.4.5, Affirma Analog/Artist Design Environment, OASIS, Multi-Process Skill, Spectre/RF |
Abstract |
The RFIC-Dynamic Link enables an integrated design flow between the Cadence IC Design Framework, DFII and the Agilent EEsof EDA Advanced Design System(ADS). With the 4.4.5 release of DFII we have evolved the integration from using the OASIS socket interface to OASIS direct netlisting, as used by Spectre/RF. This introduces several differences in the use-model and performance, which we will discuss in detail in this paper. |
Biography |
Mario Aranha is a Software Design Engineer at Agilent Technologies' EEsof EDA division. Previously he worked as a Staff Scientist at the Lawrence Berkeley National Laboratory at U.C. Berkeley and as a Memeber of Technical Staff at AT&T Bell Laboratories, Murray Hill, N.J. |
Title |
Developing Testbenches for functional verification using verilog |
Author |
Mark Azadpour |
Company |
Vitesse Semiconductor |
Cadence Tools |
verilog nc and verilog xl |
Abstract |
To assist in functional verification of chips, an automatic test bench generator was designed that supported a 4GL like language. Designers would right tests in this langauage and the test bench generator would generate the required verilog code to execrcise the chip. Various timing requirement such as parallel processing and expected data was supported in this language. This allowed the designers to directly test the functionality w/o a need for verification engineers to get involved. This concept can be expanded to support various other verification tools such as Specman etc. The ultimate goal is to avoid a need for designers to yet learn another language in order to be able to functionally verify their designs. Both verilog xl and ncsim were supported to run the final code and dump files were created to save the expected vs actual data as well as errors. |
Biography |
Author has a BS in EE/Computer engineering and a MS in EE from Ohio State Univ. He is currently working on his PhD in EE/ EDA emphasis at Univ. of Colorado. He has over 12 years of industrial experience in the Software tool development and functional verification area in various companies such as Motorola. He is currently with Vitesse Semiconductor Corporation. |
Title |
|
Author |
Daniel Aznar, Philippe Moyer, Christophe Oger |
Company |
Motorola |
Cadence Tools |
|
Abstract |
Starting with version 445, Cadence revisited the way a foreign analog simulator can be integrated in Analog Artist. While previously tied to cdsSpice socket interface for such integration, it is now possible to access the full power of native, hierarchical and incremental netlisting through Oasis Direct. As we are currently working at integrating Motorola in-house analog simulator with that methodology, this presentation will show the collaboration model we use with Cadence, how the integration went as a result, review the supported functionalities, as well as what should or could be improved. |
Biography |
Title |
|
Author |
Devin Barrett |
Company |
Cisco |
Cadence Tools |
ConceptHDL, Allegro, CheckPlus, Skill (Concept and Allegro), and library development. |
Abstract |
This paper, and presentation describes setting up a "CDS site" environment structured such that a user of the tools can easily access the tools and his/her projects, on multiple platforms, without the user maintaining multiple sets of environment files; a set for each platform. This structure also eases the administrators maintenance; modifications, to the environment, are done once. |
Biography |
Devin has 24 years in the electronics industry, with the last 15 years spent in EDA. Devin was on the International Cadence Users Group board of directors for two years. More recently, Devin was an Applications Engineer with Cadence, in the services organization, and is currently working for Cisco Systems, as the PCB Design Flow architect for the Enterprise Line of Business. |
Title |
|
Author |
Harry D. Bartley |
Company |
Tektronix |
Cadence Tools |
Concept, Concept-HDL, Allegro, chdl_uprev, Packager-XL |
Abstract |
Concept to Concept_HDL (using chdl_uprev) I. Overview of Tektronix environment and general approach to design uprev. II. Known causes of uprev warnings and errors. III. Steps and Requirements in the Uprev process. IV. Forcing association with the Allegro board. (not a Cadence recommended procedure.) V. Information related to our experience upreving designs, design sizes, design types, and time lines. |
Biography |
BA Degree in History and Industrial Arts Secondary Teaching Certificate in History and Industrial Arts Taught drafting classes for 10 years at Marysville High School, Marysville, California. Twenty-two years experience in CAD and CAE training and support. Supporting CAE tools for the past 14 years, Tektronix CAE Systems, then Mentor Graphics Schematic Capture, currently Cadence Schematic Capture tools. |
Title |
Worse Case Analysis using Analog Workbench |
Author |
Andrew Bell |
Company |
ITT Industries |
Cadence Tools |
Analog Workbench |
Abstract |
To insure that a product will meet the customer's requirements it is necessary to perform circuit analysis which will be able to predict the product's worse case performance. This can be done using circuit simulation tools like Analog Workbench in conjunction with statistical device models. This paper will attempt to show how a worse case analysis can be done using Analog Workbench and how to develop a statistical device model library. |
Biography |
I have used Analog Workbench to perform Worst Case Analysis on numerous analog circuits for the last ten years. I have also advocated the development of statistical device libraries to support various ITT products. |
Title |
|
Author |
Al Craver |
Company |
Motorola, Inc. |
Cadence Tools |
Concept,Allegro,Project Manager,Flow Manager |
Abstract |
Administering tools, processes and communications to both new and experienced tool users, across worldwide sites, is a daunting task. Varying skill levels and English language proficiency levels complicate the matter. For any solution to be effective, it must be robust, address any language barriers and be easy to use. Since many are familiar with the Internet, the Design Automation group at Motorola's Broadband Communications Sector (BCS, formerly General Instrument) chose the WEB to attack this problem. Our Intranet solution, the "Web-based Engineering Design Environment" integrates tools, processes and automation utilities to facilitate development of products that are cost effective, more reliable and quicker to market. Its point and click GUI addresses the ease-of-use concerns while use of language overlays can break down any language barriers. It enables users to be more productive by providing centralized access to the tools they need, while providing a roadmap to guide them through the design process, reinforcing what is taught in training. This roadmap delivers our "best practices" design methodology, promoting a "design it right the first time", not "design it until it's right" philosophy. To facilitate that philosophy, we will deliver data to the desktop, enabling users to make more intelligent component selection based on a variety of factors. The full potential of this solution is yet to be realized, but undoubtedly goes well beyond the scope of this presentation. |
Biography |
I am a 11+ year user of Cadence/Valid tools spanning the front-to-back tool suite of Concept through Allegro. I have been employed at Motorola's Broadband Communications Sector (formerly General Instrument)for the last 5 years. I am currently employed as the CAD architect for Cadence tools in the Engineering Tools Architecture and Development group. This role includes integrating these tools with other Enterprise tools to provide an "end-to-end" product development solution. |
Title |
A Library of Behavioral Baseband Models for Fast RF Architectural Explorations |
Author |
Jess Chen |
Company |
SpectreRF Group Cadence Design Systems |
- | |
Cadence Tools |
|
Abstract |
This paper describes a library of baseband behavioral models to help RF system designers transform system level specifications into component specifications for candidate ar-chitectures. Two kinds of models distinguish the library from conventional baseband libraries. The first kind of model simulates inductors and capacitors through a time-varying coordinate transformation. This new way of modeling reactive elements lets users simulate linear dynamic loading effects at baseband with Spectre. The second kind of model provides the RF systems engineer with DSP instrumentation that runs in Spectre. All models in the library are implemented in VerilogA. A design example is presented using the Circuit Optimizer to minimize output rms noise subject to constraints on rms output signal level and rms error vector magnitude. |
Biography |
Jess Chen received his bachelor's degree from UC Berkeley in physics and applied math in 1977. He received a Master's degrees in electrical engineering from San Jose State in 1982 and an Engineer's Degree from Stanford in electrical engineering in 1985. In 1991 Jess received a Master's degree in mechanical engineering from the University of Santa Clara. Prior to joining Cadence, Jess spent 15 years at Lockheed modeling and designing spacecraft power electronics and motor drives. For the last 5 years, Jess has worked at Cadence developing behavioral models for communications systems. Jess has been at local start up now for nearly two whole days where he is an RF systems engineer. |
Title |
Analog/mix-signal behavioral vs transistor level simulation results analysis |
Author |
G. Lamant / S. Yamauchi / M. Nogawa |
Company |
CDS & Texas Instruments Japan Ltd. |
Cadence Tools |
Skill / Analog Artist / Ocean |
Abstract |
With the advent of practical analog behavioral languages, we are seeing someevolution in the design flows used by the designers in that space. Trying to achieve the productivity of the digital design flows, they are looking at using a top-down design approach enable by such languages. While the advantages of such a method are not a question, the practical implementation of top-down design for analog/ mix-signal circuits is a real challenge. Notwithstanding the lack of usable analog synthesis, the designers are challenged by a verification problem. They need to make sure that the transistor implementation that they have created match the higher level behavioral description that was simulated previously in the system. This includes several type of analysis (transient, AC,...) and several types of measurements (voltage, current, frequency...). This paper proposes to revue our efforts to date to implement an *assisted* methodology to help the designers with that task. |
Biography |
Title |
|
Author |
Richard Munden |
Company |
Acuson |
Cadence Tools |
Concept, Allegro, SpecctraQuest, NCSim, etc |
Abstract |
I used to be frequently asked "How do I know what parts are in the library and how complete each part is?" Then I saw a demo of somebody's web base component browser and thought "Hey, I could do that!" This paper will describe the web base component browser I wrote for Acuson. It was written in perl and took only a couple of days to get to a usefull state. Of course, enhancements go on forever. The browser provides view into the componet data base to retrieve information on the Concept library, the Allegro footprint, the timing, simulation model, signal integrity model, vendor status, price, datasheets, etc. I will provide source code for parts of the program. This topic would also fit into the admin track. |
Biography |
I have been using Cadence products longer than Cadence has existed. I am currently the CAE Manager at Acuson. Previously I was a CAE Manager at TRW. I am President of the Free Model Foundry, do Cadence library consulting, and teach VHDL and VITAL modeling. |
Title |
|
Author |
Dennis Nagle |
Company |
Cadence Design Systems |
Cadence Tools |
SPECCTRAQuest, Allegro, ConceptHDL, SigXP |
Abstract |
The Constraint Manager will be a major focus of the next release and will revamp the way High Speed constraints are managed throughout the entire Design Flow. This paper will explain what the Constraint Manager is and how it operates. |
Biography |
Dennis Nagle is a Technical Marketing Manager for High Speed Systems Design and is currently responsible for Constraint Manager. He graduated with a BS EE from WPI in 1987 and since then has been involved with High Speed PCB design in various capacities. |
Title |
AN EASILY MANAGEABLE LIBRARY OF TECHNOLOGY INDEPENDENT SYMBOLS |
Author |
HOI NGUYEN |
Company |
ACUSON CORP. |
Cadence Tools |
CONCEPT, ALLEGRO |
Abstract |
This paper describes a Concept library development methodology I have been using at ACUSON Corp. This library will minimize the number of cells that need to be created and the effort required to maintain them. My presentation will cover everything from the creation of logic symbols to the structure of the information needed for cell-based PPTs, simulation models, Allegro symbols, BOM, etc. In addition it decribes how this library architechture links all the various tools used in the board design process. |
Biography |
Hoi Nguyen is with ACUSON Corp., a manufacturer and service provider of diagnostic medical ultrasound systems. He holds an A.S. in Computer Science from Boston University, Massachusetts, and has worked in the EDA industry for over 10 years. Currently working as an EDA Library Developer and Support, Hoi develops and manages the libraries of Concept and Allegro symbols used for schematic creation and PCB design. He also provides library guidelines and daily technical and tool application support, tutoring, and problem solving for Hardware Design Engineers, Manufacturing Engineers, Component Engineers and PCB Designers during the progress of schematic creation, PCB design and manufacturing. |
Title |
Top-Down Analog Design and Bottom-Up full-chip Veification with Analog Languages |
Author |
Gary Pratt |
Company |
Mentor Graphics |
Cadence Tools |
Composer, Artist |
Abstract |
Top-Down Design, and languages: They are not just for digital anymore. The ideal Analog and Mixed Signal simulation environment will allow algorithmic investigations at the system level, architectural trade-offs at the behavioral level, all detailed design at the transistor level design. This presentation will show how Mentor Graphics' integration into Artist accomplishes this with its an extensive library of building blocks (CommLib), language neutral modeling (VHDL, VHDL-AMS, Verilog, Verilog-A, C, etc); and foundry support for transistor level simulation. See also how the same behavioral models used during Top-Down design are ideal for optimization and subsequent full-chip mixed-signal verification of an entire multi-million transistor design. |
Biography |
Gary Pratt has been the with Mentor Graphics since 1997, and currently serves as the Technical Marketing Manager for the Analog and Mixed Signal product group. He is a graduate of the University of Wisconsin - Madison, a Member of IEEE, and a licensed Professional Engineer who has been practicing for 18 years. Mr. Pratt's career experience includes the design and design management of cardiac image processing hardware, multi-threaded image processing software, and high voltage/high current PWM amplifier systems. He has been an enthusiastic user of EDA tools for analog and digital; system, board and IC level design and verification since 1982. You can reach Mr. Pratt at gary_pratt@mentor.com |
Title |
|
Author |
James T. Roberts |
Company |
Motorola |
Cadence Tools |
DFII, Composer, HNL netlister |
Abstract |
To shorten the design cycle, circuit designers have found it desirable to estimate their circuits' performance on-the-fly, as they create their schematics. Even with Cadence's tight integration of the DFII environment with other tools, it is still necessary to generate a netlist and run a separate tool to run many basic timing analysis functions. This is overkill for many situations. With the methods presented here, it is possible to estimate delays and leakage power on-the-fly for individual paths, by selecting a net in the schematic and hitting a hotkey. Known methods are borrowed from other CAD tools and ported to SKILL for determining paths, fanout, schematic-level parasitic extraction, and basic static timing analysis; thus obviating the need for netlists and spawning other processes. SKILL programmers can then customize the procedures to suit their technologies and return results to circuit designers within 2 seconds. |
Biography |
James T. Roberts holds a Master's in Electrical Engineering from Georgia Tech, and has been a CAD Engineer for microprocessor designs since 1995. During his career at Intel, he worked on the Pentium Pro, Pentium II, and Pentium III processors, managing the Cadence tools, CAD environment, and RTL simulation jobs. He is currently employed at Motorola in Austin, TX, working on the PowerPC G4 and later designs. |
Title |
|
Author |
Adam Sherer |
Company |
Cadence Design Systems |
Cadence Tools |
SPW and VCC |
Abstract |
Mobile phones. Cable modems. Digital video cameras. Automotive control systems. The Signal Processing Worksystem (SPW) and the Virtual Component Co-design (VCC) environment are the Cadence products that enable the system-level design of these complex products, but what exactly do these products do? This question will be answered with a technical introduction to these products with the goal of creating a SIG in the Cadence User Group among you and your peers. |
Biography |
Adam Sherer has bachelors degrees in electrical engineering and computer science and a masters in electrical engineer. Adam's career has included analog simulator design at Analog Devices and five years of applications engineering at Cadence in the digital IC and board simulation focus areas. Most recently, Adam has been working in Cadence Marketing involved with VHDL simulation, HDL model packaging, and system-level IP marketing. |
Title |
|
Author |
John Wright and Dwayne Sherrard |
Company |
AMI |
Cadence Tools |
|
Abstract |
|
Biography |
Title |
Verilog-AMS Mixed-Signal Simulator |
Author |
Richard Trihy |
Company |
Cadence Design Systems |
Cadence Tools |
Spectre, NC |
Abstract |
This paper describes a Verilog-AMS based mixed-signal simulator and its application to the modeling and simulation of mixed-signal systems. Traditionally mixed-signal simulators consisted of "glued" solutions where 2 or more different simula-tors with different netlist languages communicated through a backplane. Consequently circuit partitioning of the design into partitions (and design representations) suitable for the different engines was required a priori, before the invocation of the simulator. Also the conversion of signals between domains and simulators required netlist modification with the insertion of interface elements. However with the advent of a single mixed-signal language, Verilog-AMS the design representation can be uniform, and the partitioning performed by the simulator. In addition the design of more sophisticated interface elements enabled by the powerful Verilog-AMS language and their automatic insertion by the simulator bring a new level of flexibility and power. This paper will describe the architecture of the new AMS simulator and the application of its Verilog-AMS language to the simulation of analog and digital circuits. The event sensitivity and time synchronization features that enable accurate modeling of complex mixed-signal interactions will be described. Special focus will be given to unique Verilog-AMS modeling techniques for analog, digital and mixed-signal circuits. For example the continuous-time or "analog" constructs of the language can be used to accurately model not just analog but also digital circuit behavior. In addition the discrete-time or "digital" language constructs often allows efficient simulation of analog circuit behavior. Examples of these and other modeling techniques will be presented. |
Biography |
Richard Trihy received the PhD degree in electrical and computer engineering from Carnegie Mellon in 1993. His PhD was in the area of circuit simulation techniques. In 1994 he joined Cadence as a member of the R&D staff working on the Spectre circuit simulator, with particular focus on analog and mixed-signal behavioral language capabilities. Presently he is an engineering Director in the Mixed-Signal R&D group. In this capacity he manages the San Jose development teams for the Spectre and AMS simulator. |
Title |
|
Author |
Jean Q. Xia, Sabita Pilli, Yingchun Yang |
Company |
Cadence Design Systems, Inc. |
Cadence Tools |
Affirma ATS |
Abstract |
To verify very large CMOS designs with a reasonable speed without losing accuracy, event-driven circuit simulation becomes crucial in many applications. Applications such as transistor- level timing and power analyses/optimization using circuit simulators, require the simulators to be dynamic, fast repeatable, and integrable in an embedded fashion. This paper presents the architecture and the features of an embedded, dynamic event-driven circuit simulation system, as an extension of Cadence ATS-fast MOS technology. The system provides a comprehensive solution for dynamic, fast repeatable and embedded simulation. As a dynamic simulation system, the method we implemented involves a break-point insertion in event- driven algorithm, enabling stop/continue and callback scheme. For fast repeatable simulation we developed a master-circuit based approach to avoid circuit re-loading and initialization costs. As an embedded system, an object layer was created around the simulation engine, API's were developed for all basic aspects of simulation interfaces, and the system was built as libraries integrable at object-code level. An application on this embedded dynamic simulation system: transistor-level timing analysis/optimization presented a successful story of a practical solution. 1. Introduction With the growing need for accurate simulation on very large circuits (>100K transistors), event-driven circuit simulators have evolved and presented excellent trade-off between accuracy and speed. Affirma ATS-fast MOS is one such simulator. Its dynamic regionization and event-based algorithm provide fast yet accurate simulations (<5% accuracy and 10-50X faster v.s. SPICE). In recent years, applications such as timing/power analyses/optimization requiring transistor-level accuracy have begun to use circuit simulators as computational engines. During these analyses, a large number of simulations must be performed which involve a lot of data exchange and post-processing for further analysis. Thus there is a need to develop dynamically controllable, parameterized and fast repeatable simulators which can be tightly embedded into the application software. The work described in this paper extended the ATS-fast MOS engine to achieve this goal. The key new features of the system are: a dynamic simulation control mechanism through a break-point insertion algorithm; a master-circuit based approach for fast repeated simulations; parameterization; and a complete API interface. A break-point insertion algorithm and a callback scheme associated were implemented to allow the application to control, stop and continue simulation in a dynamic manner, based on post- processed results. A master-circuit based approach allows the application to select and simulate specific blocks of pre-loaded/initialized circuitry, allowing rapid repeated simulations without the overhead of loading/initializing parts of the circuit not required in current analysis. The simulator was also extended to be parameterized and an object layer was added around the ATS-fast MOS core, which enable the application to dynamically set/alter device parameters and design values between multiple simulations. To tightly embed the simulation system into applications software, API's for all basic aspects of simulator interfaces were developed, such as for setting/altering device parameters/ design values; setting initial/fixed voltages; applying stimulus; setting simulation options; monitoring specific nodes; controlling & repeating simulations; and retrieving outputs, all on-the-fly. A successful application of this system is the transistor- level timing analysis used in core characterization/optimization, where both accuracy and speed are critical. This system is used as the computational engine replacing Elmore delay model in delay calculations. The experimental results were based on three groups of large designs (Latches, Domino, Custom Cells) from Cadence Austin Design Center. For each circuit in each design group, the longest path characterized by this system was also simulated with SPICE worst-case conditions. The comparison results are within 5% v.s. SPICE with much faster run times. |
Biography |
Jean Q. Xia: Over 12 years EDA research and development experiences. Over 10 years experiencs in Cadence. Currently, a Senior Member of Consulting Staff in Cadence R&D, Custom IC Group. Has been working on the areas of mixed-signal simulations, mixed-signal design-for-testability, custom IC design capture, mixed-signal floorplanning, etc. 1993 winner of Cadence Best Technical Paper Award. Special Achievement Award of Cadence, 1995. Educations: B.S.E.E., Peking University. M.S.E.E., University of Pittsburgh. and 1.5 years of Ph.D. program in E.E., University of Pittsburgh |
