Title |
|
Author |
Jian Bao |
Company |
Intel |
Cadence Tools |
DesignSync, DesignSync DFII |
Abstract |
A difficult challenge in the migration from Cadence 4.3 to Cadence 4.4 is the lack of Data Management (DM) tool. Synchronicity Corporation introduced its DesignSync* tool, which not only has a DFII interface for all Cadence applications but also has the capability to handle all non-Cadence data. This presents an excellent opportunity to put both digital and analog design data under one DM tool and utilizes one set of automation scripts to administer data from both sides. The new design methodology in FPG(Flash Product Group) addresses performance issues, access control issues, and reduces confusion for the user by eliminating unnecessary graphic interfaces. The new methodology takes advantage of the new capabilities of DesignSync* and sets up a consistent DM environment for digital, analog, and collateral development teams. The approach that will be presented at the demo session uses a directory structure that is consistent at root level for digital, analog, and collateral design teams. The automation scripts that have been developed takes full advantage of the inheritance nature of DesignSync* . So once a workspace is setup, there is no need for any user to specify any DM information. On the Cadence tools side, DesignSync* offers too many graphic interfaces. This not only confuses users, but also makes customization difficult. The approach that will be presented at the demo centralizes the graphic interface. The new interface simplifies number of options and choices. It minimizes user errors and gives the administrator the opportunity to choose the fastest implementation of each operation. On the non-Cadence tools side, DesignSync* also provides a graphic interface. Again this interface displays too much information and allows too much freedom for the everyday designer. The demo will show a set of customized commands that allows users to interact with the DM data with efficiency. The third area of application is for the collateral team that works on libraries, rules files etc. The demo will show an approach that allows collateral team members to use DM for their work. The demo will also show the conventions for releasing data on AFS to the design community and multi-site users. Also, the demo will show how the digital, analog, and collateral area will handle their release processes interacting with this new DM tool through tag features. On the security side, the presentation will show how to use the built-in access control feature from DesignSync to realize control at the levels of working group, library, cell, view, and DM operations. The presentation will also show how to use access control to work with the ECO/LCO process at different stages of project. |
Biography |
Jian Bao has a Masters Degree in Electrical Engineering from the University of Wisconsin at Madison, and presently works as a senior design engineer for Intel in Folsom, California. Job duties have ranged from CAD Development, logic design. |
Title |
|
Author |
Paul N Bompastore |
Company |
Texas Instruments |
Cadence Tools |
ITKDB/DFII |
Abstract |
This paper will demonstrate through example how I used the Cadence ITKDB to port an application written in C from Viewlogic to Cadence. The application is an ESD Checker which reads the Cadence schematic database, and analyzes various electrical ESD rules. Originally the application was written for Viewlogic's Powerview Framework using the C API called Viewbase. I will show the approach I took to port the application in a short period of time. I will outline tradeoffs of the ITKDB as it compares to other C API's such as Viewbase. I will also summarize key points that users need to know about if they plan to use the ITKDB for C application development. |
Biography |
Paul N Bompastore MSCS: Boston University BSCS: North Adams State VLSI State-Of-The-Art: Northeastern University Texas Instruments Merrimack NH Tools and Technology manager responsible for EDA infrastructure development/support. Over 16 years of EDA experience ranging in various technical development positions and management responsibilities. Primary focus at TI is analog mixed signal IC design flows. |
Title |
|
Author |
Kyla Cragg |
Company |
Cadence Design Systems |
Cadence Tools |
All |
Abstract |
This paper and presentation describes the problems and causes of poor software messages in Cadence products. The Message Improvement Initiative (MII), jointly created by Support, Usability, and Publications, formed to determine what could be done to address this issue. Documentation of "cryptic" software messages, message writing guidelines for R&D, and a message review process are just a few examples of projects underway that are destined to make using Cadence products easier in the future. |
Biography |
Kyla Cragg is a senior technical writer in SP&R at Cadence Design Systems. Along with currently leading the Message Improvement Initiative, Kyla has been active on the Customer Contact Network - a Publications initiative aimmed at training writers and editors on developing skills to find out more about customer documentation needs. She co-authored a paper entitled "First Contact - Talking to Your Documentation Users", which was presented at the 1998 International Conference for the Society for Technical Communication (STC) and a 1999 meeting of the Silicon Valley chapter of the STC. The paper also won a 1999 Merit Award in the Northern California Technical Communication Competition. |
Title |
|
Author |
Peter Dudley |
Company |
International Business Machines |
Cadence Tools |
DFII, Composer, Virtuoso, ITK |
Abstract |
As designs increase in size and complexity, it becomes necessary to have a fast way of traversing the design's hierarchy and extracting information from it. This "design hierarchy" information is sometimes needed by tools which run outside of Cadence (ie. design auditing) and by circuit designers. This paper presents a simple ITK program, cdbSearch, which traverses a cell view's hierarchy and extracts information from it. A comparison of the performance of cdbSearch versus a similar Skill program on various parts of a large next generation server processor design will be given. |
Biography |
Peter Dudley is a Staff Engineer at IBM who's responsibilities include design auditing, tool development and other design environment issues for IBM's new Power4 microprocessor. |
Title |
A New Method for Electronic Software Distribution and Installation |
Author |
Hariraj Dyal / Scott Baeder |
Company |
Cadence Design Systems |
Cadence Tools |
Applies to ALL products |
Abstract |
Electronic Software Distribution (ESD) is becoming the norm for Independent Software Vendors (ISVs) in almost all segments of the Software Industry. In the EDA industry, sheer size of the data, product configuration requirements, frequent updates, interoperability issues, multiple platforms and entitlement issues cause problems in packaging, distributing and installing EDA Software. All of these challenges have not been adequately addressed by the ESD solutions currently in use. With the rapid advent of Business-to-Business portals, it is important that EDA adopt a new method for ESD. In this paper we describe a next generation approach to ESD. We enumerate the prior packaging, distribution, installation and configuration issues and discuss how the new ESD solution addresses them or minimizes their impact. |
Biography |
Hariraj Dyal has a Masters in Computer Science. He worked for Cadence for 6 years on software packaging, distribution and installation prior to founding "Khanpur Technologies". Khanpur is in the process of developing a next generation Software Distribution and Installation Solution. Scott Baeder has been with Cadence Design Systems for over 11 years and has held a number of positions in the areas of Configuration Management, Licensing, and Installation. He is currently the Architect for Licensing and Installation, and is helping define the next generation systems for e-commerce, license delivery and software installation and distribution. |
Title |
SDM : A SMARTCARD SECURE DATA MANAGEMENT SYSTEM, BASED ON CLEARCASE AND OPUS 4.4 |
Author |
GAILLARD Christophe, SANCHEZ Jean-Marie |
Company |
STMicroelectronics |
Cadence Tools |
Opus 4.4 |
Abstract |
This paper describes the ClearCase configuration management put in place over the Opus 4.4 environment, in the STMicroelectronics SmartCard Product Development. First Opus 4.4 had been chosen rather than Opus 4.3 because its data format is a pure Unix file system, suitable for an external data management system. Then ClearCase from Rational was selected as a robust and professional tool, fulfilling the certification requirements for SmartCard circuits. An interface between ClearCase and the schematic and layout editors has been developed, so that basic actions such as checkin and checkout can be performed directly in Opus. A complete environment has been created to secure the way ClearCase is used, based on hierarchical configuration specifications. A ClearCase configuration specification (CS) is a version filter, allowing the user to select either a given frozen release (tag) of a library (explicit selection), or to develop inside an isolated version branch (implicit selection). The hierarchy in CS makes possible to assemble a product with some blocks, each selected from a tagged library. A same version (tag) of a library can be used in several products in a safe and certifiable way, making IP Reuse a reality. ClearCase among other functions allows a designer to work in the same library within different contexts (branches), and allows as well several designers to work concurrently on the same library and context (checkout conflict management). The way ClearCase is used in SmartCard team, poses some performance problems, due to the strict access control implemented for the design. However its advantages for tracking differences between versions and for managing concurrent developments, lower the impact of performance. The future developments on the current environment include mainly the improvement and automation of database administration, and the improvement of performance. |
Biography |
Title |
|
Author |
Steve Knepper |
Company |
Analog Devices |
Cadence Tools |
DFII: Composer, Virtuoso, etc... |
Abstract |
In this paper I will discuss experiences ADI has had working with various Design Management options, in particular: TDM, VersionSync, and DesignSync DFII. All options have their strengths and weaknesses which I will try to summerize and compare. ADI started using TDM early in 1997. We quickly discovered that it was way too complicated to be used by our designers and set about to customize it. Various customizations were made which I will present, but to summerize here: GUI for creating projects and workareas, GUI for access control, library search routines, conversion utilities, "Show Checkouts" command, and many more. Although these features made TDM useful, we soon discovered that it was not robust. I will present some of the bugs we've found, workarounds we've made, and code written to check a library. Given the poor nature of TDM, we decided to explore other options. We were one of the first sites to try VersionSync. We found it more robust but more limited. I will explain some of the limitations here (no dynamic workareas, no access control) and some of the recent work that is occuring at ADI to overcome these limitations (access control GUI and workarea mirroring). We also did a formal evaluation of Synchronicity's DesignSync DFII. We found it much more powerful, but quite expensive. However, even it is imperfect and I will discuss some of it's flaws, and features here. I will finish the talk by briefly mentioning some of the other options that are available. ADI has not thoroughly evaluated these tools, but I plan on researching them prior to the talk. |
Biography |
I have been at ADI working in various CAD roles for 5 years. During this time I have been focusing in two areas 1) Cadence DFII including 4.4 conversion, DM, netlisting, CDF, etc. 2) Digital Design Methodology including the latest Cadence TDD flows Prior to this I worked for 2 years at Advanced Microelectronices (now part of Cadence Design Resources) in Jackson, MS. I was working on automating standard cell creation and characterization. This work was presented in 1995 ICUGC. MSECE from Carnegie-Mellon University in 1993 BS Physics and Engineering Physics from Eastern Nazarene College in 1991. |
Title |
Design Simulation and Application Resource Management Combine to Reduce EDA's Time-to-Market Pain |
Author |
Alex Lynch |
Company |
Platform Computing |
Cadence Tools |
Ambit, Verilog, Verifault, Analog Artist, QuickTurn |
Abstract |
The problems confronting designers of electronic systems are becoming increasingly complex. Chip and component density expands, clock speed increases, operation voltage decreases, testing and product quality must be faultless to avoid disaster, and operational expenses must be minimized. Collectively, these factors make the designer's job enormously difficult. To make matters worse, time-to-market demands mandate that designs be brought profitably to market before the underlying technology becomes outdated. As a result, computer tools are used increasingly to expedite the design process, to reduce reliance on costly physical prototypes, and to automate verifications. With such increased reliance on computers for design and verification, there has been an attendant increase in the use of hardware description languages (HDLs). Unfortunately, the use of HDLs for describing field programmable gate arrays (FPGAs) requires high computational capacity to maximize the benefits of EDA software tools. To overcome increased design complexities and tighter product development schedules, the following tools are being tapped: · Faster event-based simulators · Parallel (as opposed to serial) simulation · Better EDA methodologies · More powerful workstations · Optimized use of resources through Workload Management |
Biography |
Alex has been in EDA software marketing for over 15 years with companies like Mentor Graphics, IBM/PCAD, Daisy Systems, and VeriBest. He is currently a Strategic Relations Manager for Platform Computing, Inc. the makers of LSF, the worlds leading application resource management and load balancing product. |
Title |
A Powerful Non-Recursive Skill Program for Cell View Traversal |
Author |
Robert D. Morel |
Company |
International Business Machines |
Cadence Tools |
DFII |
Abstract |
The shortage of tool developers, and the numerous requirements placed on the complex chip designs being developed today, dictate the need for very customizable programs. A program for cell view traversal is no exception. The primary objective for traversing the hierarchy of a cell view is to collect information about it. However, because there are so many data collection scenarios possible, it is difficult to write a single traversal program capable of satisfying every need. This paper presents a program that attempts to solve this problem by allowing for user-defined functions that can extract the desired cell view information, and even control the traversal process. The traversal algorithm is non-recursive, thereby minimizing the memory requirements of the program. |
Biography |
Robert Morel is a staff engineer for the IBM Corporation in Hopewell Junction, New York. He is currently working on the Power4 microprocessor project. His primary duties are tools development and maintenance. |
Title |
|
Author |
Yolanda M Pirez |
Company |
Motorola |
Cadence Tools |
SKILL |
Abstract |
This paper will attempt to give an overview of SKILL as a programming language. Some of the basics of any programming language will be presented. Then a comparison of SKILL to other languages such as LISP, C, C++ and Java will be presented. A brief overview of object oriented programming will also be covered. This paper ought to provide a better understanding of the SKILL/SKILL++ language. |
Biography |
Title |
|
Author |
Pitchumani G |
Company |
Wipro Technologies |
Cadence Tools |
|
Abstract |
Cadence tools administration in a multiple version environment is getting complex due to user preference to particular version. Updates and patches are released by cadence often. Installing the same without affecting the projects is a concern area. Customizing the tools with scripts to check for multiple floating licenses could enhance effective utilisation of the licenses. The tracking of the license usage with tools like Flexadmin/SAMSuite could ease the load on administrators to decide on additional licenses especially in a FAM environment.Tracking the user problems and making them available in an intranet site could reduce the time spent in solving the problem again. Reducing License downtime and license renewal before the expiry dates could avoid productivity loss for projects. Tracking overloaded servers would help decide the redistribution of load and thereby enhance effective utilisation of licenses. The LSF tool would help create server farm for load balancing. The common .cshrc settings for a user could help a new user to start with the project directly and reduce time spent on Openbook tutorials. |
Biography |
Education : Bachelor of Engg (B.E) in Electronics and Communication from Regional Engineering College , Tiruchirapalli, TamilNadu, India. Worked for 3.5 Years in Intergraph/Veribest products as AE for PCB/Verification tools. Working for 3.5 Years in EDA Tools administration in Wipro on the tools from following vendors: Cadence/Mentor/Modeltech/Synopsys/Leonardo/Xilinx/Altera/Summit/Viewlogic |
Title |
|
Author |
C H Sakharwade |
Company |
Cadence Design Systems (I) Pvt. Ltd. |
Cadence Tools |
new functionality |
Abstract |
With the increased focus on time-to-market, design reuse is expected to become common. While doing system level design, designer would typically look for previous designs that could be used partially or fully. This may be at module level or board level (partial logical block within the board should also be permissible). In the context of design reuse, it becomes necessary to store the reuseable module information with a set of attributes. This would help the retrieval of such objects based on a user specifed criteria before reuse can be attempted. Broad level classification of the modules can be done so that user does not have to search across too large an object set (this could happen easily in a big enterprise where hundred's of designs are done every year). Such a classification would have to be intutive (Digital/Analog/Mixed, CPU/Interface /Network/Memory). Note that the set of attributes would be unique for a given lowest level classification). A typical query to such a catalog would be based on the prior knowledge of classification that user is expected to have (a naive user could query such a system to familiarize with the classification before querying the database). In order to catalog, it becomes necessary to define a set of attributes. For this, one would take a look at the functionality to arrive at a minimum attribute set that would help differentaite amongst such designs. For example, for CPU based modules, following attributes would help the search: i) CPU Type (68060, Pentium-III, Celeron, ...) ii) DRAM Size (16 MB) iii) SRAM Size (1 MB) iv) Boot PROM (256 kB) v) Cache Size (512 kB) vi) CPU Clock Speed (200 MHz) vii) MIPS Rating (150 MIPS) viii) Network Interface (Y/N) ix) Video Interface (Y/N) x) Real Time Clock (Y/N) xi) Max Operating Temp (50 Cel) xii) Min Operating Temp (0 Cel) xiii) Design Intent Reference (path to a document hierarchy) Similar attribute set may be defined for different category of module. All the attributes should have a predefined legal values or ranges and the associated unit of measure (ex: SRAM Size would have legal range from .125 MB to 16 MB). |
Biography |
|C. H. Sakharwade is a Senior Member of Consulting Staff at the PCB Systems Division Business Unit of Cadence Design Systems, NOIDA , India. He did his M. Tech. in Advanced Electronics from IIT Madras. He has more than 21 years of experience in Electronic System Design, Component Information Systems, and Electronic Design Automation. His primary area of interest are Signal Integrity, High Speed Design and system design.. He has previously worked with TIFR, CDOT, and Aspect Develoment, Inc. |
Title |
|
Author |
Shiv Sikand |
Company |
Silicon Graphics Inc |
sikand@sgi.com | |
Cadence Tools |
DFII |
Abstract |
An ultra high performance DM solution for Cadence DFII 4.4 Current DM solutions for Cadence do not meet the need of many customers and have proved to be a major roadblock in 4.4 migration. The available systems offer versioning through unsophisticated archiving software such as RCS and lack SCM (Software Configuration Management) features long available to software developers. This paper describes an SCM based approach to Design Management for Cadence 4.4, utilizing Perforce's Inter File Branching mechanism and follows Industry Best Practices for SCM. Perforce is rapidly gaining market share in the software world due to it its ultra high performance, scalability, low cost and powerful SCM features. This paper describes how this technology can be applied to the hardware design process to deliover a truly integrated approach for all aspects of the design flow. The SGI/Perforce solution is being released under the OpenSource model and empowers companies to customize and build their DM system according to their needs rather than a prescribed formula. |
Biography |
Shiv Sikand is in the Microprocessor Group at SGI and has been working on advanced CAD methodologies for full custom and ASIC design for the past 10 years. He received his BS and MS degrees from the University of Manchester in Physics and EE. |
Title |
A WAN Based Design Anywhere Environment for Application and Project Data |
Author |
Jacob Skolnik |
Company |
Motorola |
Cadence Tools |
|
Abstract |
As projects get more complex and engineers become more scarce, the need for a comprehencive design anywhere environment becomes an essential part of many design organization. This paper outlines some key capabilities of the current CAD environment we are using at CESWITC in Motorola. This includes: 1) All project data under DM control across the WAN 2) All applications installed only once and replicated. 3) All environment data for applications and projects under DM control 4) All computers using common kernal disk images. This paper will also cover some major road blocks and our plans for the future. |
Biography |
Jake is IC Design Automation Manager at Motorola with the Personal Subscriber Sector. |
Title |
A New Method for the Distribution and Management of licenses |
Author |
Sashi Subramanian / Scott Baeder |
Company |
Cadence Design Systems |
Cadence Tools |
Applies to ALL products |
Abstract |
Electronic licensing has long been used to protect EDA software. As more and more software is purchased, the sheer number of licenses, frequent updates, interoperability issues, and the need to provide better management of the software assets are all issues that must be addressed. Many of these challenges have not been adequately addressed by the current systems used to distribute and manage these licenses. With the rapid advent of Business-to-Business portals, it is important that new, web enabled systems be developed. In this paper we describe a next generation approach that will provide the customer with the capability to initially configure the products they have purchased using a web based interface. It also provides the license administrator the flexibility of transferring their licenses between different license servers (re-assigning) or to move the license server from one machine to another (re-hosting). By using customer specific entitlement, authorization, privileges and digital certificates, this system can automate the process without compromising on the customers privacy and security. One added benefit is that by implementing this system, we will also enable the customer to collect usage data and securely collect it in a central data store for later data mining and analyses. |
Biography |
Sashi Subramanian has a BS in Computer Science and has been with Cadence Design Systems for over 7 years. He has been working with licensing technology for the past 5 years. Scott Baeder has been with Cadence Design Systems for over 11 years and has held a number of positions in the areas of Configuration Management, Licensing, and Installation. He is currently the Architect for Licensing and Installation, and is helping define the next generation systems for e-commerce, license delivery and software installation and distribution. |
Title |
|
Author |
Graham Taylor |
Company |
Philips |
Cadence Tools |
|
Abstract |
Over the last few years tool and hardware administrators at Philips have been faced with several problems: Increase the productivity of IC designers by allowing them to spend more time on design and hence improve time to market.
A standard design environment has evolved based on shared computer resources controlled by load balancing software. Selection of tools and libraries is controlled by a locally developed package and standard wrapper scripts are provided that set the correct environment for each tool. Designers can select tool and library versions they need without knowledge of where they are installed or their required environment. This is now standard across all Philips IC design centres and is providing the basis for developing methods for successful multi-site working. |
Biography |
