International Cadence Usergroup -

Title	Design Reuse
Target Audience	Design Engineers interested in enabling reuse of their company's IP.
Speaker	Steve Durrill
SIG	SCD
Abstract	This session covers all the steps required for a complete design reuse methodology. This includes the finer details of the process implemented using Concept HDL, Packager-XL and Allegro. Details of the methodology Demonstration of the flow Explanation of how it was implemented Enhancements in the PE14.0 release How Reuse of IP reduces time and cost of designs How Reuse Enables Top-down approach to PCB Designs How Reuse Coordinates multiple site engineering through methodology and infrastructure
Speaker Biography

Title	Verilog AMS
Target Audience	Design Engineers interested in language based design with Verilog-AMS and CAD/Modeling Groups interested in creating interface elements for the new AMS Designer product from Cadence.
Speaker	Jon Sanders
SIG	SCD
Abstract	System on chip (SOC) has made lots of news over the past few years yet the impact of analog on these chips is requiring new solutions. Leveraging off of the existing Verilog-D (IEEE 1364) and Verilog-A (OVI) standards a new language has been developed called Verilog-AMS. This language is uniquely suited to help designers of complex mixed signal blocks and MS-SOC as they address the issues of these designs. Extensions to Verilog to describe behavior other than digital are included in the Verilog-AMS Language Reference Manual (v2.0), currently available from Open Verilog International (now called "accellera"). Analog only simulators have been provided based upon the OVI LRM are available now and simulators with analog and digital capability are in development. The tutorial on Verilog-AMS will present an overview of Verilog-A and describe in detail the extensions added to support Verilog-AMS. Example uses of these extensions will be present throughout the tutorial. Understanding of this new language is critical to gain the benefits of the Cadence recently announce AMS Designer product and products being announce by other vendors.
Speaker Biography	Jon Sanders (Chair of Verilog-AMS technical workgroup)

Title	Allegro Skill
Target Audience	Allegro Skill For designers and administrators who use the Allegro, Specctra Quest, and APD tools. Some programming experience required. SKILL is a programming language that is very much like LISP and C.
Speaker	Dave Palumbo
SIG	PCB
Abstract	The Allegro SKILL tutorial is a brief introduction to the programming interface available in the Allegro and APD products. The tutorial will introduce the functionality that is available through SKILL so the user can gain an understanding of the type of programs and commands that can be written. The tutorial will use many examples to show real world examples of functionality that can be implemented with the SKILL programming language.
Speaker Biography	Dave Palumbo is from the Educational Services group at Cadence Design Systems, Inc.

Title	High Speed 101
Target Audience	For designers of high frequency and fast lead/trailing edge signals that use Allegro, Specctra Quest, and APD.
Speaker	Todd Westerhoff
SIG	PCB
Abstract	Introduction to transmission line theory and how it affects PCB design, signal integrity design issues and terminology, examination of crosstalk and its effects on PCB design, common design techniques for signal integrity and introduction to CAD tools.
Speaker Biography

Title	IC Skill
Target Audience	CAD Support
Speaker	Suzanne M. Kahn
SIG	System Administration
Abstract	This Skill tutorial will be two basic parts applicable to dfII: Part One: SKILL features introduced in version 4.4.5 dfII to customize the working environment in the CIW, cell windows and forms. Part Two: New functionality with ROD commands Creating shapes from existing shapes, Defining and using stretchable handles, Creating abutable pcells.> ROD Features in the Layout Editor GUI - Multipart path form - ROD-aware shape creation forms (rectangle, path, polygon) - ROD-aware property editor form SKILL-level ROD Features - Creating shapes from existing shapes. ROD in Parameterized Cells - Defining and using stretchable handles - Creating abutable pcells for Virtuoso-XL ROD Pcell library
Speaker Biography	Suzanne is a Lead Consulting Engineer for Methodology Services at Cadence Design Systems Inc.

Title	IC 443/445 Update
Target Audience
Speaker	Dave Wagner
SIG	System Administration
Abstract	IC 443/445 is an update tutorial about what are the changes from 443 to 445 as well as highlights of what's new in IC446. An overview of the changes in DFII including the System Configuration Checking tool. Virtuoso Schematic Composer updates including GUI changes, incremental symbol modification, and other miscellaneous changes. Training on the use of VersionSync, an easy-to-use design management system for samll LAN-based design teams. SKILL changes, including new, deleted, or modified SKILL functions and now to request SKILL audits.
Speaker Biography	Team Leader for the DFII/Skill Customer Support group. He has over 15 years of experience supporting customers with Cadence tools. His experience includes applications services, application engineering, pre-sales and post-sales support.

Title	Diva/Dracula to Assura Migration
Target Audience	End Users and Rule Deck creators
Speaker	Nalayini Gunan
SIG	IC
Abstract	Assura has been developed to be compatible with Diva rules and the Diva use model and provide both interactive and batch verification capabilities. This tutorial will use the Diva to Assura migration guide as the basis for the tutorial. Additional insights and observations learned from customer engagements will be included in the tuturial. The tutorial will review rule compatibility, use model compatibility, Skill customization, and integration of Assura into the Analog Artist flow. The tutorial will cover the complete product migration from Diva DRC, LVS, LPE/PRE to Assura DRC, LVS, and RCX. In addition, the tutorial will highlight many of new capabilities of Assura that can improve productivity for full custom and analog design verification, including antenna checks, short location, and hierarchical error debugging. Since many Diva users also have Dracula verification, a brief overview of the Dracula to Assura migration process will be presented. This tutorial should provide a significant jump start helping Diva users interested in reducing verification cycle times and improving extraction capabilities for new processes to be able to successfully manage the migration process to the new Assura physical verification tools.
Speaker Biography	physical verification core competency team Experinece: physical verification core competency team for the past year and in Education Services for 9 years. Her experience includes training, post-sales support and consulting services on the Design Framework II infrastructure and physical verification tools. She has been actively involved in the Cadence User Group in the past especially in getting users involved and gathering feedback during the Design Framework II 4.3.4 to 4.4 migration period.

Title	CCAR/VCR/VCD Tutorial
Target Audience	End User
Speaker	Peter Karpinski
SIG	IC
Abstract	The CCAR/VCR/VCD tutorial will encompass 5 tutorials from which students can choose to exercise. VCR top level constraint driven routing Transistor level routing Interactive topology editor including virtual_pin Interactive bus routing Virtuoso custom designer (VCD) tutorial There will be four instructors available: Peter Karpinski - Custom IC VCD core comp engineer (Lead instructor) Jack Wild - Custom IC VCD core comp engineer Ken Pavloff - Custom IC applications engineer, San Jose Sales Office Trina Phan-Vu - Custom IC applications engineer, San Jose Sales Office
Speaker Biography	Peter Karpinski - PC designer from 1975-1995. Owned PC design full service bureau. Worked as a consultant with major Bay Area electronic companies. Joined CCT as QA PC Specctra router engineer. Started supporting IC Craftsman in 1995. Performed QA, AE, training, demo and tutorial development duties. Currently in ACPD Core Comp mainly responsible for all types of technical support of VCP/VCR/CCAR including VXL. Education: UCSB 1965-1970. BA in Anthropology. 1 year graduate school in secondary education.