International Cadence Usergroup

ICU 2000
ICU 1999

2000 International Cadence User Group Conference

Schedule - Sunday, September 10, 2000

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7:00 -8:00
Continental Breakfast for Tutorial Students
8:00 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
	Design Reuse	Allegro Skill	Diva/Dracula to Assura Migration	IC Skill

12:00 - 1:00
Lunch on Your Own
1:00 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
	Verilog AMS	High Speed 101	Virtuoso Custom Router v10. and Virtuso custom designer Workshop	IC 443/445 Update

6:00 - 9:30
Conference Registration and Social Hour

Schedule - Monday, September 11, 2000

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7:00 -9:00
Continental Breakfast and Opening Session Opening remarks: Ray Bingham President and CEO, Cadence Design Systems Keynote address: Peter Shwartz author of the "Long Boom" presents a view of the next 20 years "Sorry, We Can't Accomodate Autographs"
9:00 - 9:45
Cadence Executive Panel Members To Be Announced
9:45
Break
10:00 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
10:00	SIG Opening Remarks and Top 10 Issues Review and new top 10 issues list compilation	SIG Opening Remarks and Top 10 Issues Review and new top 10 issues list compilation	SIG Opening Remarks and Top 10 Issues Review and new top 10 issues list compilation	SIG Opening Remarks and Top 10 Issues Review and new top 10 issues list compilation
10:15
10:30
10:45			DYNAMIC - A Java based Toolset for Integrating Dynamic Logic Circuits Into A Standard VLSI Design Flow
11:00	Worse Case Analysis using Analog Workbench
11:15		What's new in 14.0
11:30	Top-Down Analog Design and Bottom-Up full-chip Verification with Analog Languages		Bitstacking With Only A Composer Schematic Editor License
11:45

12:00 - 12:45
Lunch
12:45 - 1:45
Cadence Keynote address: To Be Announced
1:45 - 2:00
Break
2:00 - 5:15
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
2:00	PCB FE Road Maps IC FE Road Maps (2nd room TBA)	Road Maps: PCB SPECCTRA SPECCTRAQuest Advanced Packaging Allegro	SP&R (Synthesis Place and Route) Technical Road Map	Systems Administration Road Map
2:15
2:30
2:45			Physical Verification Roadmap
3:00
3:15
3:30	Break
3:45	PCB Front End Technical Panel	Technical RoadMap Q&A	Assura RCX Tech Panel	A New Method for the Distribution and Management of licenses
4:00
4:15
4:30				Technical Panel: License
4:45
5:00

5:15 - 6:00
Break
6:00 - 9:30
Cadence Product Demonstrations

Schedule - Tuesday, September 12, 2000

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7:15 -9:00
Breakfast Special Guest Speaker: Sally Ride America's first woman in space "Sorry, We Can't Accomodate Autographs" Breakfast available at 7:00 Sponsored by: Sun Computer
9:00 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
9:00	Concept to Concept_HDL (using chdl_uprev)	Advanced Specctra Techniques	Pegasus: making dfII application fly over the Genesis infrastructure	A Fast Non-Recursive ITK Program for Cell View Traversal
9:15
9:30	Another Web Based Component Browser			Using The ITKDB - A User's Example
9:45			Generating a High Voltage Dmos Pcell with ROD
10:00	Break	Physical Design Checking and Simulation Model Verification with Specctraquest		A Powerful Non-Recursive Skill Program for Cell View Traversa
10:15	Web-based Engineering Design Environment		Break
10:30		Break	ROD Evaluation for Analog BICMOS Technologies	Break
10:45		WEB Based Collaborative IC Package Design
11:00	Introduction to Constraint Manager		Layout Synthesis Using ROD	An Analysis of SKILL as a programming language
11:15
11:30		3rd Party In	Virtuoso Custom Placer the placer for ACPD
11:45

12:00 - 1:00
Lunch & ICU Board Nominations
1:00 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
1:00	Introduction to System Level Design Tools	IBIS documentation, library management and user support at 3Com Carrier R&D	UTMC Gate Array Cell Generator using Cadence Relative Object Design	A WAN Based Design Anywhere Environment for Application and Project Data
1:15
1:30	Developing Testbenches for functional verification using verilog		Virtuoso XL Constraint Manager and its roll in ACPD	Design Management: The good, the bad and the ugly
1:45		PCB TBD
2:00	Pre-Layout Schematic Timing Estimation		HFC ToolBox: A number of utilities for the a Full Custom Hierarchical Designv	Break
2:15		Comparison of SI Simulation Results and Lab Measurements: A Forensic Case Study		Implementing DesignSync with Cadence and non-Cadence data
2:30
2:45	Break			SDM : A SMARTCARD SECURE DATA MANAGEMENT SYSTEM, BASED ON CLEARCASE AND OPUS 4.4I
3:00	Verilog-AMS Mixed-Signal Simulator	Integrating Allegro and Mechanical Design Using IDF	Cross Probing for Every Desk Top
3:15				Advanced OpenSource Design Management for 4.4
3:30	Analog/mix-signal behavioral vs transistor level simulation results analysis		Analysis of Transmission Line Effects on IC's
3:45
4:00	A Library of Behavioral Baseband Models for Fast RF Architectural Explorations	Customizing the Allegro Environment	VCD Panel	DM Technical Panel
4:15
4:30
4:45

5:00 - 9:00
Vendor Fair Drinks & Hors d'oeuvres will be served

Schedule - Wednesday, September 13, 2000

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7:00 -9:00
Breakfast Steve Mangelsdorf Senior Engineer/Scientist at HP's PA-RISC microprocessor design lab in Ft. Collins, Colorado Design challenges for future high performance computer systems Breakfast available at 7:00, sponsored by Hewlett Packard Speaker at 8:00
9:00 - 12:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
9:00	Creating a Custom Site Environment for Cadence PSD tools	PCB Design Flow Optimization	Very Deep SubMicron Issues	Design Simulation and Application Resource Management Combine to Reduce EDA's Time-to-Market Pain
9:15
9:30	Top Down Mixed Signal Design Flow Using Cadence Tools	Linking Cadence PCB Tools to a Product-Data Management System	Design for Manufacturing/Yield - Redundant Via/Contact Insertion Tool	The Cadence Message Improvement Initiative
9:45
10:00	Break
10:15	Cataloging for Design Reuse (session with SYSTEM ADMINISTRATION SIG)	Review of Manufacturing Formats and what they mean to you	Analog Design Synthesis	Cataloging for Design Reuse (session with SCD SIG)
10:30
10:45	Integrating an in-house IC analog simulator through Oasis Direct		Break	Tools Administration
11:00		Specctra Expert Panel	Formal Methods in Functional Verification of Circuits: An Overview
11:15	ADS RFIC-Dynamic Link using OASIS direct			The Philips IC Design Environment
11:30			X-Terminator: A hierarchical pin placement optimizer
11:45

12:00 - 1:00
Lunch & ICU Board Nominations
1:00 - 5:00
	Systems & Circuits Design SIG	PCB/MCM SIG	IC SIG	Systems Administration SIG
1:00	An Embedded, Dynamic Event-Driven Circuit Simulation System As an Extension of Cadence ATS-fast Technology	Allegro Expert Panel (includes half hour discussion on Designing without DRC's in Allegro)	Design kit for high performance SiGe technology	Sig Business/Top 10 Issues
1:15
1:30	Simulation Tech Panel
1:45			Next Generation Analog Design Flow	Break
2:00
2:15		Break
2:30	Analog IC Frontend panel	Expert Shapes	Physical Knowledgeable Synthesis (PKS) Technical Panel
2:45
3:00
3:15		Top 10 Issues for next years voting and SIG chair voting
3:30	SIG Selections and SIG Top 10 Intake
3:45			SIG Selections and SIG Top 10 Intake
4:00
4:15
4:30
4:45
5:00
5:15
5:30 - 9:00	Cadence Fun Night

Go To: Top / Sunday / Monday / Tuesday / Wednesday

2000 International Cadence User Group Conference Schedule - Sunday, September 10, 2000

Conference Registration and Social Hour

Schedule - Monday, September 11, 2000

Cadence Product Demonstrations

Schedule - Tuesday, September 12, 2000

Vendor Fair

Schedule - Wednesday, September 13, 2000

Steve Mangelsdorf

Design challenges for future high performance computer systems

Cadence Fun Night

2000 International Cadence User Group Conference

Schedule - Sunday, September 10, 2000