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ICU 2000
ICU 1999


IC
PCB
SCD
SA


Greetings Fellow Cadence Users:

Only 7 more days to submit your abstract to become a part of the best users group in the EDA industry. We need your technical papers in the PCB, IC, System Design and System Admin arenas. To encourage participation we, have an outstanding offer:

Submit an abstract or convince a friend to submit an abstract and you will have your conference registration fee waived ($550 Value).

(Free registration is for accepted and scheduled abstracts. Rejected abstracts will not be entitled to the free registration.)

http://www.cadenceusers.org/conferences/icu2001/CFP2001.html Call for Papers URL

http://www.cadenceusers.org/2001/abstract_submit.htm" Submit Abstract

http://www.cadenceusers.org International Cadence Users Group URL

Joe Morrison, Chairman, International Cadence Usergroup

2001 International Cadence User Group Conference
September 16-19, 2001
DoubleTree Hotel, San Jose, California


  • The independent INTERNATIONAL CADENCE USER GROUP seeks technical papers for the 2001 International Cadence Users Conference to be held in San Jose, California.

  • The aim of the conference is to provide users and administrators of Cadence products with a forum for the exchange of both technical and non-technical information in the areas of acquisition, installation, configuration, and design using Cadence products.

  • Highlights of the conference:
    • Technical papers by users
    • Tutorials and training sessions by industry experts and Cadence trainers
    • Networking with other designers, tool administrators, technical managers, and Cadence employees
    • Third-party vendor exhibits
    • Panel sessions
    • Cadence Executive Panel
    • Q&A sessions with technical experts(fellow users and Cadence engineers)
    • Live Cadence product demonstrations and roadmap presentations
    • High-interest keynote speakers

  • Suggested paper topics include:

    • System and IC
    • Tool integration including 3rd party vendor software and internally constructed tools
    • Design methodology aids using Cadence Skill or Integrator's Toolkit
    • Mixed signal design flow
    • Circuit and behavioral simulation using Verilog-A, Verilog, VHDL or spectre
    • Design Kit development for CMOS and mixed-signal technologies
    • Design for manufacturability tool development and utilization
    • Library Development using ROD PCells
    • Benchmarks for performance, usability and functionality for Cadence tools vs. other vendors' software
    • Data translation (EDIF, PIPO, LEF/DEF)
    • Migration issues of Cadence tools and databases
    • Physical Verification experience with Assura
    • Open Library API for synthesis
    • Automated custom placement and routing
    • Top-down design techniques
    • System on chip construction
    • System level design
    • Intellectual property management
    • Software installation methods and stream release management
    • Platform support (Linux, Solaris, HP-UX, AIX, NT)
    • Cadence support using Virtual Private Network / Collaboration environment
    • Post-layout simulation
    • PKS design flow
    • Clock-tree synthesis techniques
    • Configuration and Design Management (CM/DM) for tools and design data
    • Archiving techniques for design data and tools
    • Power optimization and scan insertion using BuildGates

    PCB Systems
    • Concept techniques, Process and Design Flows
    • Orcad Capture Techniques, Process and Design Flows
    • Core Allegro Techniques, Process and Design Flows
    • Specctra DO file construction, routing strategies and techniques
    • High-speed and Signal Integrity techniques
    • High-density interconnect design techniques
    • Library development and verification
    • Simulation of PCB schematics (Verilog or VHDL)
    • Constraint Management
    • Hierarchical design methodologies
    • Schematic capture with high pin count devices
    • Data management solutions for schematic capture, or library
    • RF Design solutions
    • Variant design methodologies
    • Design input-3rd party, Concept, Orcad Capture, Mechanical
    • Placement-manual, automatic, design reuse, Design for Assembly
    • Routing-manual, automatic, design reuse, Signal Integrity
    • Design Output-postprocess automation, fab, assembly, mechanical

Papers will be presented in 30 or 45 minute time slots. Longer time slots may be arranged if the topic warrants. Presenters who meet the July 21, 2001 paper submission deadline will receive a full registration discount($550 value) and free admittance to one tutorial of their choice.

Authors are required to submit an abstract not exceeding 250 words by APRIL 15th, 2001. Electronic submittal of abstracts is preferred. Submit abstracts through the ICU web site at: http://www.cadenceusers.org/2001/abstract_submit.htm

Include the following information with all abstract submissions: a title, a list of the Cadence products to which it pertains, your name and job title, company name and address, telephone and fax numbers, email address, speaker biography, estimated time required for presentation and type of audio/visual aids required.

Authors of accepted abstracts should ensure they have the necessary company permission to publish the information described in the abstract and paper, and authorization to present the paper at the conference. Abstract information, including author's name and company may be published in print or web form by the ICU for the purpose of promoting the conference. Papers and Presentations received by the due date will be included in the Conference Proceedings.

Questions on topic suitability or logistics welcome: icu_info@cadenceusers.org or (480)596-9377. The ICU Web site is http://www.cadenceusers.org/

Summary of important dates:

Abstract deadline:

April 15, 2001

Paper submission deadline:

July 21, 2001

2001 Cadence User Group Conference:

September 16-19, 2001