International Cadence Usergroup - ICU 2001 Monday Schedule

2001 International Cadence User Group Conference

7:30
Continental Breakfast
8:00
Welcome from the ICU board, general announcements
8:15
Cadence Design Systems Keynotes Overall company strategy, technical strategy, customer support, customer advocacy (downstairs : General Session)
10:00
Break
10:30
Cadence Design Systems Executive Panel
12:00 - 1:00
LUNCH

1:00 - 5:00
SIG :	IC	SCD	SA	PCB	PCB	Support & Education
1:00	IC Sig Business	SCD Sig Business	Compute Platforms Sunrays in a Compute Ranch Environment	Road Maps Allegro Specctra	Road Maps Capture, Concept Front-to-Back Utilities	Find the Information You Need - Without Calling the Hotline
1:15	DFII Technical Pane	DFII Technical Pane
1:30			HP Partitioning of large ASIC Simulations on HP Hardware
1:45				Specctra Quest APD	IPSD	iLS - IBM Experiences with Cadence Internet Learning Services
2:00			Distributed processing in the Analog Design Environment
2:15	Break	Break
2:30	Custom IC Road Maps CIC Roadmap	Digital IC Road Maps Synthesis Place & Route Roadmap	Break	Break	Break	Break
2:45			Technical Panel: Is Linux for real in EDA? Cadence position statement, panel discussion (participants representing Cadence, Sun, HP, IBM, Intel. Tim J. Ellerbruch and others	Allegro Top 10 Issues Review	Front End Top 10 Issues Review
3:30				Technical Panel	Technical Panel
4:00	Break	Break		Break	Break
4:15	Constraint Driven Analog Synthesis in the VCD Flow using NeoCell	Removing the SDF Handcuffs: OLA Delay Prediction		Front-to-Back Flow Technical Panel	Front-to-Back Flow Technical Panel
4:30
4:45	Generating Electrically Correct Layout in a Next Generation Analog Synthesis Flow

5:00 - 9:00
Cadence Design Systems Demo Cocktails & Hors d'oeuvres