2001 International Cadence User Group Conference

Schedule - Tuesday, December 4, 2001

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday

7:30

Breakfast

8:00

Sun Microsystems Sponsored Keynote
John Brennon
VP of Sun Hardware Engineering
Enterprise Systems Products
Motivational Talk for the Attendees
Downstairs General Session

8:00 - 12:00
 

IC

IC

SCD

PCB

PCB
  PCELLS
 IC Front End
 System Level Design
 Specctra
 PSD Front-End Tools
9:00 An Automatic Physical Design for High-Performance Analog Circuits        
9:15 Introduction / Welcome Introduction / Welcome
9:30 The Effects of MOSFET Foldin
on Device Performance		 Homemade Spice Import-Export Methodology Routing Strategies for Today's Ultra-dense High Speed Designs Importing Implemented FPGAs to ConceptHDL based board design
9:45  
10:00 SKILL Procedure Development for Pcell Abutment Advanced Spectra Techniques
10:15 Behavioral Modeling in Simulation of PLL's for SOC applications Break ConceptHDL based VHDL FPGA FLow
10:30 Break JPEG-2000 Modeling millennium image compression standard in SPW
10:45 A Versatile and Robust Method of Communications with Pcells
11:00 Break Break Break
11:15 Pcells / Verification & Regression Testing

Testing Pcell, A Lesson in Problem Solving		 Introducing AMS Designer into a Production Design Flow Modeling the IEEE 802.15.4 Physical Layer Roadmap / Technical Panel Enhanced Cross-Referencing Solution for PCB Schematics
11:30
11:45    
 

12:00 - 1:00

LUNCH

1:00 - 5:00

 

IC

IC

SCD

PCB

PCB
1:00 A Modular System for Regression Testing of Physical Verification Rule Deck Process Design Kits

A SiGe LNA Design Example using IBM SiGe technology ADS Dynamic Link in CDS 		  PSD Back-End Tools

THALES solution for PCB design Flow optimization		 Concept & Constraint Manager
1:15
1:30 Regression Testing of Feature Rich Pcells and Their Flows A Mixed Signal Cadence Design Kit for High Voltage CMOS Applications  An Introduction to System Level Modeling in SystemC 2.0 Improving Design Quality and Robustness
1:45 Allegro Forward and Back annotion Process with Viewlogic Schematic Capture
2:00 Custom Place & Route

X-CON: A Hierarchical Wiring Resource Management Utility
Integrating VCC System-level design and State of the Art State Machine
2:15 Break
High Speed Analysis

Modeling and Optimizing a Power Delivery System (PDS) in the frequencly domain
2:30   Analog Mixed
Signal Front End Pane

Analog Mixed Signal Front End Panel
 Break Break
2:45 New Allegro SKILL GUIs for Fun & Profit
3:00 Break Break
 
3:15 Virtuoso Custom Designer: A Custom Physical Design Using SpecctraQuest for Signal Integrity Simulations
3:30 A Tool for Characterization and Analysis of Custom Cells in the Analog Simulation Environment  Improving Verification with RTL Emulation Use Programmable Keypad to Accelerate Design
3:45 Virtuoso Custom Placer: Interactive and Automated Custom Placement
4:00
NC AMS Applications 		 Test Stimulus Transformation for TestBuilder Test Benches Implementing The NewGrid Functions for Displaying Report Results Crafting a Custom SPICE-based Analysis Environment for High Speed Design
4:15 VCD Technical Panel
4:30   Functional Verification of a Differential Operational Amplifier Signal Integrity Interconnect Analysis/Routing using Constraint Manager
5:00 Break

5:30 - 9:00

VENDOR FAIR

Sponsored by:  


Go To: Sunday / Monday / Tuesday / Wednesday / Thursday