2001 International Cadence User Group Conference

Schedule - Wednesday, December 5, 2001

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday

8:00

Continental Breakfast

8:00 - 12:00

 

IC

IC

SA

PCB

PCB
  Synthesis Place and Route
 Backend Verification Post Layout IP, Configuration and Design Packaging Design Manufacturing
8:45       Chip IO Planning for Optimum Package Design Creating Probe Fixtures for Board Debugging
9:00 TLF4x Library Generation and Verification Methodology Considerations for Global Distribution of IP Blocks
9:15 Integrating Allegro Mechanical Design Using IDF
9:30 Extending Static Timing Capabilities For Full-Chip Verification Using Dynamic Simulation Test Vehicle Automation Chip and Package I/O Planning and Co-design
9:45 Developing and Deploying a Multi-Site IC Design Project Environment
10:00 LPS: A Step Towards Power Closure Producing physical verification decks with minimal resources Designing with no Design Rule Check Violations in Allegro
10:15 Break Break
10:30 Break Break Using Relational Database to track and manage a WAN based Design Spider Route - A Topological Package Router
10:45 Break
11:00 Datapath Synthesis in Ambit BuildGates Macro-Cell DIVA for Rapid LVS Verification   Determining PCB Cost Schedule without losing your shirt
11:15
11:30 Contrasting Different PKS Design Flows Custom Verification using DIVA and DFII  
 

12:00 - 1:00

LUNCH

1:00 - 5:00
 

IC

IC

SA

PCB

PCB
1:00 On the Relevance of Wire Load Models Parasitic Extraction and Simulation Methodology for A 4Mbit SRAM A Concurrent language for capturing chip design flow: Verilog Ipi - A PCB-level static timing analyzer Getting the most out of IEEE 1149.1 boundary scan (JTAG) testing and on-board programming
1:15
1:30 Scan Chain Insertion, Optimization, and Rule Checking using BuildGates Mask Data Preparation Flow using Assura THALES answer to complex EDA infrastructure management 
1:45 Benefits of an Electronics Engineering Integrated Environment across multi-site development
2:00 Break Break Break
2:15 SP&R Technical Panel Physical Verification Technical Panel Multi-site Development Integration -- Bugs, Locations, Branches, Code and Builds Break Quality/SKILL

Using automated tools to quickly produce process test chips
2:30 Putting Design Re-Use to Work in Your PCB Product Design
2:45 Break Yet Another Cadence 4.3 to 44 Migration Story
3:00 Open Discussion on Configuration Management and Design Management Automating the ConceptHDL Library Verification Process
3:15 Cadence Code Quality - Cadence/IBM Joint Project
3:30 Break Concurrent & Team Design Concept/Allegro
3:45 Next Generation Physical Implementation Solutions Are Necessary To Solve Very Deep Submicron Design Challenges    
5:00 Break

5:30 - 9:00




Cadence Customer Appreciation Night &
Most Valuable Paper Ceremony

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday