2004 International Cadence Usergroup Conference

Schedule - Monday, September 13, 2004

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday

7:00 - 5:00 PM - Foyer
Conference Registration
7:00 - 8:00 AM - Ballrooms C-D-E-F
Breakfast
8:00 - 8:30 AM - Santa Clara Convention Center Theater
Welcome from the ICU Board and General Announcements
Donna Ducharme, ICU Chair
8:30 - 8:45 AM - Santa Clara Convention Center Theater
Opening Remarks

Michael J. Fister,
President and Chief Executive Officer
8:45 - 9:30 AM - Santa Clara Convention Center Theater
Keynote Speaker

Ted Vucurevich, Senior Vice President,
Office of the Chief Technology Officer

Special Drawing for ICU Attendees: Segway HT
(ICU Board members and Cadence employees are not eligible)
9:30-10:00 AM - Foyer
Break
10:00-11:30 AM - Santa Clara Convention Center Theater
Panel Discussion

Cadence Executive Panel
11:30 - 12:30 PM - Ballrooms C-D-E-F or Outside
Lunch
12:30 - 4:00 PM
Room: Lawrence
San Tomas
Lafayette
Stevens Creek
Cypress
Bayshore West & East
Winchester
SIG: IC #1 IC #2 IC #3 Sys Admin PCB
Theme: Spec Driven Environment Accelerated Layout
Digital IC System Administration Allegro Platform Roadmaps
ICU Host: Steven Klass Anna Votino Hisham El-Masry James Roberts Andy Kulik
12:30   Deliver EDA Projects On Time, On Budget Using Software License Management
12:30 - 1:00		 PCB SIG Welcome
12:30 - 12:45
12:45 Frontend Roadmaps
12:45 - 1:45
1:00 Platform/OS, Licensing and Installation Technical Panel
1:00 - 2:00
1:15
1:30 Spec Driven Roadmap
(Aptivia, Artist, NeoCircuit)
1:30 - 2:00		 Using Synthesis in Big A, Little D Chips
1:30 -2:00		 Cadence Encounter Platform Technology Roadmap
1:30 - 2:30
1:45 Allegro PCB Editor / Router and Allegro Package Design Roadmaps
1:45 - 2:45
2:00 Schematic Pcell Implementation in Virtuoso Platform
2:00 - 2:30 		Accelerated Layout Roadmap (VLE, VXL, VLM, CCAR)
2:00 -3:00		 Automated Installation and Distribution of Cadence Software
2:00 - 2:30
2:15
2:30 Break
2:30 - 3:00 		Alternative Flip Chip methodologies in First Encounter
2:30 - 3:00		 Break
2:30 - 3:00
2:45 Break
2:45 - 3:15
3:00 TFT Design Verification with UltraSim
3:00 - 3:30		 Virtuoso Preview: The floorplanner for custom and mixed designs with Rectilinear Block Features
3:00 - 3:30 		Leakage Power Optimization flow
3:00 - 3:30		 Design Anywhere! - Mobility Solution for Silicon Design
3:00 - 4:00
3:15 Allegro PCB SI (SpecctraQuest) Roadmap
3:15 - 3:45
3:30 Custom Netlist Procedures in AMS Designer
3:30 - 4:00		 Automated Custom Physical Design (ACPD) Flow in Cadence IC5.0.x for Mixed-Signal designs
3:30 - 4:00		 Implementing Power Management IP for Dynamic & Static Power Reduction Using SoC Encounter™ at 130 nm
3:30 - 4:00
3:45  
4:00 - 7:00 PM- Ballrooms A thru H
Cadence Technology Night

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday