Continental Breakfast for Tutorial Attendees - Foyer |
| 8:00AM - 12:00PM |
| Room: |
Camino Real |
Alameda |
Bayshore East |
San Tomas |
Central |
Lafayette |
Bayshore West |
| Instructor: |
Dennis Rockwood
Cadence Design
Systems, Inc. |
S. Dharmarajan
Cadence Design
Systems, Inc. |
Marko Chew
Cadence Design
Systems, Inc. |
Ken Tseng
Trisha Kristof
Cadence Design
Systems, Inc. |
Ted Paone
Cadence Design
Systems, Inc. |
Juergen Hartung
Cadence Design
Systems, Inc. |
Ron Voglesong
Cadence Design
Systems, Inc |
8:00
-
12:00
|
High Speed PCB Design Using Allegro PCB Router (SPECCTRA) |
Allegro PCB Librarian |
Introduction to Optimize Feature in VXL and VLE-Turbo 5.1.41 |
Hands-on Workshop: Managing Signal and Power Integrity in the Digital IC Design Flow |
Open Access Adoption and Migration |
Complete Wireless Design Flow described for a WLAN 802.11a/g Application |
Intro to Behavioral Modeling and the Verilog-AMS language |
Mid-Morning Break for Tutorial Attendees - Foyer |
| 12:00 - 1:00PM |
| Lunch
- on your own |
| 1:00 - 5:00PM |
| Room: |
Camino Real |
Alameda |
Bayshore East |
San Tomas |
Central |
|
Bayshore West |
| Instructor: |
Dennis Nagle
Cadence Design
Systems, Inc. |
Dave Palumbo
Cadence Design
Systems, Inc. |
Suzanne Kahn
Cadence Design
Systems, Inc. |
Ken Tseng
Trisha Kristof
Cadence Design
Systems, Inc. |
Eric Leavitt
Cadence Design
Systems, Inc. |
|
Ron Voglesong
Cadence Design
Systems, Inc. |
1:00
-
5:00 |
Advanced Constraint Manager |
Advanced Allegro SKILL |
SKILL Advanced Programming Techniques |
Hands-on Workshop: Managing Signal and Power Integrity in the Digital IC Design Flow (continued) |
OpenAccess C++ API |
|
Analog & Mixed Signal Modeling Techniques |
Mid-Afternoon Break for Tutorial Attendees - Foyer |
| 6:00 - 9:30PM |
Rooms: Lobby West - Terrance / Cabana |
| ICU Registration
& Reception |
