2004 International Cadence Usergroup Conference

Schedule - Tuesday, September 14, 2004

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday

7:00 - 5:00 PM - Foyer
Conference Registration
7:00 - 8:00 AM - Ballrooms C-D-E-F
Breakfast
8:00 - 8:15 AM - Santa Clara Convention Center Theater
Welcome from the ICU Board and General Announcements
Donna Ducharme, ICU Chair
8:15 - 9:15 AM - Santa Clara Convention Center Theater
Keynote Speaker

Steve Schulz,
President and Chief Executive Officer
Click here for Keynote Abstract
9:15 - 9:30 AM - Foyer
Break
 
9:30 - 12:00 PM
Room: Lawrence
San Tomas
Lafayette
Cypress
Bayshore West & East
Camino Real
Winchester
Stevens Creek
SIG: IC #1 IC #2 Sys Admin IC #3 PCB #1 PCB #2
Theme: Spec Driven Environment Accelerated Layout
Open Access Digital IC Allegro PCB Editor SKILL (Allegro SKILL) Allegro PCB SI (SpecctraQuest)
ICU Host: Steven Klass Anna Votino / Bashar Nazanda James Roberts Hisham El-Masry Charlie Davies Carl Musetti
9:30 Survey on Inductor Simulation and Design Methodologies
9:30 - 10:30		 Achieving Intent of the Simulated Design in Layout Using VXL Enabled Capabilities
9:30 - 10:30		 OA Roadmap
9:30 - 10:30		 Managing Signal Integrity in Nanometer Design
9:30 - 10:00		 Effectively Using Skill in the Allegro PCB Environment
9:30 - 10:30		 Best Practices for High Speed Digital PCB Design
9:30 - 10:30
9:45
10:00 Cell Delay and Noise Models : A Survey
10:00 - 10:30
10:15
10:30 Break
10:30 - 11:00		 Break
10:30 - 11:00 		Break
10:30 - 11:00		 Break
10:30 - 11:00		 Break
10:30 - 11:00		 Break
10:30 - 11:00
10:45
11:00 Specification-Driven Technical Panel
11:00 - 12:00		 Utility for Finding and Modifying Repeated Cell Placements in Custom IC Design
11:00 - 11:30		 OpenAccess 2.2 Moving to the Future
11:00 - 12:00		 Making Timing Analysis more Monotonous
11:00 - 11:30		 Automated Checking of Spacing Between Non-Etch and Soldermask objects in Allegro
11:00-11:30		 Implementing Design Intent with Topologies and Signal Explorer
11:00 - 11:30
11:15
11:30 ZenTime and PKS/SOC Encounter: The Renesas Experience 11:30 - 12:00 High Performance Clock Design
11:30 - 12:00		 Managing Dynamic Shape properties in Allegro 15.x
11:30-12:00
11:45 IBIS Model Quality Document
11:30 - 12:00
12:00 - 1:00 PM - Ballrooms C-D-E-F or Outside
Lunch
1:00 - 5:00 PM
Room: Lawrence
San Tomas
Lafayette
Cypress
Bayshore West & East
Camino Real
Winchester
Stevens Creek
SIG: IC #1 IC #2 Sys Admin IC #3 PCB #1 PCB #2
Theme: Mixed Mode Simulation Accelerated Layout
Open Access Digital IC Allegro PCB Editor (Allegro) Allegro PCB Router (SPECCTRA)
ICU Host: Sue Strang Anna Votino / Bashar Nazanda James Roberts Hisham El-Masry Charlie Davies Randy Bye
1:00 Mixed Mode Simulator Roadmap (AMS, Spectre, UltraSim)
1:00 - 1:30		 Advances in Global Synthesis
1:00 -1:30		 New Library Options in OpenAccess 2.2
1:00 - 2:00		 Effect of Grounded vs. Floating Fill Metal on Parasitic Capacitance
1:00 - 1:30		 Modernization of the NC Drill Environment
1:00 - 1:30		 Ghost busters Update & Getting no unconnects "as SHORT as POSSIBLE"
1:00 - 1:45
1:15
Allegro Design Entry CIS (Capture)
1:30 AMSUltra: A New Mixed-Signal Circuit Simulator
1:30 - 2:00		 Export Preparation
1:30 -2:00		 Low Power Design Techniques For Leading Edge Chips
1:30 - 2:00
Corporate Data Management using OrCAD CIS (Component Information System) Option
1:30 - 2:00
1:45 Correlating Constraints between Allegro, Constraint Manager, Allegro Signal Integrity - and the Allegro Autorouter (SPECCTRA)
1:45 - 2:30
2:00 FastSPICE Circuit Simulation in Analog Design Environment
2:00 - 2:30		 Automated Layout Generation, Placement and Routing of Analog Designs
2:00 - 2:30		 OpenAccess Technical Panel
2:00 - 3:00		 Routing Through Complexities of Nanometer Design
2:00 - 2:30		 Methodology for Simulating Non Linear Magnetics with PSpice
2:00 - 2:30
2:15
2:30 Comparison of Time Domain and Frequency Simulators for RFIC Applications
2:30 - 3:00		 Towards An Open Flow
2:30 - 3:00		 IC Digital Technical Panel of Experts
2:30 - 3:30		 OrCAD Capture Designing Techniques
2:30 - 3:00		 High Pin Count BGA routing Techniques
2:30 - 3:15
2:45
3:00 Simulating Complex RF/Mixed Signal Designs using UltraSim
3:00 - 3:30
Enhance Design Productivity With XStream
3:00 - 3:30		 PSpice Model of the Hubble Space Telescope Electrical Power System
3:00 - 3:30
3:15  
3:30 - 3:45 PM
Break
3:45 -4:45 PM - Santa Clara Convention Center Theater

John Cooley
Don't miss the industry-wide survey results when he
presents "Cadence: The Good, the Bad, and the Ugly"
4:45 -7:45 PM - Ballrooms A-B-C F-G-H

Vendor Fair

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday