2004 International Cadence Usergroup Conference

Schedule - Wednesday, September 15, 2004

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday

7:00 - 4:00 PM - Foyer
Conference Registration
7:00 - 8:00 AM - Ballrooms C-D-E-F
Breakfast
 
9:30 - 12:00 PM
Room: Lawrence
San Tomas
Lafayette
Cypress
Bayshore West & East
Camino Real
Winchester
Stevens Creek
SIG: IC #1 IC #2 Sys Admin IC #3 PCB #1 PCB #2
Theme: Mixed Mode Simulation Accelerated Layout
Open Access SKILL PDK Development & Verification Allegro Package Designer (APD) Allegro Design Entry HDL and Data Management
ICU Host: Steven Klass / Hisham El-Masry Anna Votino / Bashar Nazanda James Roberts / Sue Strang Donna Ducharme Randy Bye Carl Musetti
8:00 An Migration Methodology for Process Re-targeting a Legacy Data Converter in DSM Technology
8:00 - 8:30		 A method for automating the creation of shielded busses
8:00 - 8:30		 A pcells library and routing tool giving designers the option of a DFM approach.
8:00 - 8:30 		From Concept to Composer and back again - Adventures in Schematic Translation
8:00 - 9:00 		External DRC Checking for APD
8:00 - 8:30 		Library and Design Data Management for Board-Level Designs
8:00 - 8:30
8:15
8:30 Mixed-Mode Simulation Technical Panel
8:30 - 9:30		 The Methodology and Implementation of Automatic PCell and ACPD Flow Q&A
8:30 - 9:00 		A Singular Approach to Cadence Tool Customization
8:30 - 9:00 		RF Module Design Process for IC Packaging using Agilent ADS with Cadence APD
8:30 - 9:30 		Allegro Design Workbench - A "Work-in-Progress" Data Management solution for PCB designs
8:30 - 9:30
8:45
9:00 Generating LVS and RCX Test Structures with PAS
9:00 - 9:30		 A Formal Verification Methodology for a Fully Abutted Hierarchical Design
9:00 - 9:30		 The New Layer-Boolean Functions In IC5.1.41
9:00 - 9:30
9:15
9:30 Intellectual Property Protection with Encryption
9:30 - 10:00 		CIC Physical Design Panel
9:30 - 10:30		 IBM Server Open Access Adoption Plan
9:30 - 10:30 		Automated Front-end Primitive Library Verification System
9:30 - 10:00 		3D Modeling of Stacked Die
9:30 - 10:00 		Design Reuse - Beyond the Basics
9:30 - 10:30
9:45
10:00 Power Optimization with Global Synthesis
10:00 - 10:30 		A Guide to Developing an Automated and Comprehensive Library QA Methodology
10:00 - 10:30		 How to Design a MCM with APD
10:00 - 10:30
10:15
10:30 Break
10:30 - 11:00		 Break
10:30 - 11:00 		Break
10:30 - 11:00		 Break
10:30 - 11:00		 Break
10:30 - 11:00		 Break
10:30 - 11:00
10:45
11:00 Incisive Roadmap / Techpanel
11:00 - 12:00 		DFM Roadmap
( Physical Verification, Parasitic Extraction, Power Analysis )
11:00 - 12:00		 All The Small Things: Improving productivity by leveraging SKILL on oft-overlooked problems
11:00 - 11:30		 PDK Standardization: the OpenKit Initiative
11:00 - 12:00		 Advances in the Allegro® Platform Documentation
11:00 - 11:30 		Understanding and Reducing the Complexity of high pin-count FPGA and PCB designs
11:00 - 12:00
11:15
11:30 An efficient model of SKILL coding for process sensitive custom utilities
11:30 - 12:00
11:45
12:00 - 1:00 PM - Ballrooms C-D-E-F or Outside
Lunch

Special Drawing for ICU Attendees: IBM ThinkPad (ICU Board members and Cadence employees are not eligible)
1:00 - 5:00 PM
Room: Lawrence
San Tomas
Lafayette
Cypress
Bayshore West & East
Camino Real
Winchester
Stevens Creek
SIG: IC #1 IC #2 Sys Admin   PCB #1 PCB #2
Theme: Analog Front End Accelerated Layout
IC SKILL  
Allegro Platform Technical Panels
ICU Host: Sue Strang Bashar Nazanda James Roberts  
Andy Kulik
1:00 Analog CAD Executives (ACE)
1:00 - 1:30		 A Comprehensive Verification Methodology for Analog/Mixed Signal Designs Using Assura
1:00 - 1:30		 SKILL Program, PCELL and rules deck development under a technology driven OPUS Environment
1:00 - 1:30 		 
SPB Front-End Tools Technical Panel (Including Top 5 Review)
1:00 - 2:00
1:15
1:30 OpenAccess based Framework for Rapid Analog Design Flow Integration
1:30 - 2:00 		Coding Rule Sets to improve Assura DRC/LVS performance
1:30 - 2:00 		Advanced Techniques with Qcells Abutment & SKILL Interfaces
1:00 - 1:30		  
1:45
2:00 Integrating Mathematica with OpenAccess for Advanced Circuit Analysis
2:00 - 2:30		 Assura/Diva LVS flow using Artisan 0.13 Sage-X Library in IBM CMRF8SF
2:00 -2:30		 A set of bounding-box processing SKILL procedures useful in placement optimization of wafer scribe-line features
2:00 - 2:30		  
2:15
2:30 A tool and methodology for ac-stability analysis of continuous-time closed-loop systems
2:30 - 3:00
 Making the Leap from Diva to Assura – Who Should Go There and Why
2:30 - 3:00		 Current Capabilities of SKILL as an OpenAccess ASCII representation
2:30 - 3:00		  
2:45
3:00 Break
3:00 - 3:30		 Break
3:00 - 3:30 		Break
3:00 - 3:30 		Break
3:00 - 3:30
PCB SIG Elections
3:00 - 3:15
3:15
Break
3:15 - 3:30
ICU Hosts:
Andy Kulik
Randy Bye
ICU Hosts:
Carl Musetti
Charlie Davies
3:30 New Spectre/RF Front-End enables SPICE Compatibility and High Performance Advanced Device Modeling
3:30 - 4:00 		Silicon Analysis Techpanel
3:30 - 4:30		 Automatic PCell Documentation Extraction
3:30 - 4:00 		 
3:45 Allegro PCB SI (SpecctraQuest) Technical Panel
(Including Top 5 Review)
3:30 - 4:00 		Allegro AMS Simulator (PSpice) Technical Panel
(Including Top 5 Review)
3:30 - 4:00
4:00
SIG Wrap-up / Elections
4:00 - 4:30 		  Allegro PCB Router (SPECCTRA) Technical Panel
(Including Top 5 Review)
4:00 - 4:30 		APD Technical Panel
(Including Top 5 Review)
4:00 - 4:30
4:15
4:30 - 5:00 PM
Break
5:00 - 6:00 PM - Santa Clara Convention Center Theater

Cadence Response to customer input,
"Cadence: The Good, the Bad, and the Ugly"
6:00 - 6:30 PM - Santa Clara Convention Center Theater

Conference Wrap-up and Awards Ceremony
MVP & Survey Drawing

Go To: Sunday / Monday / Tuesday / Wednesday / Thursday