IC SIG - 1999 Top Ten Issues

The Integrated Circuits Special Interest Group provides Cadence users, tool developers, and EDA support people with opportunities to enhance their knowledge of, and effectiveness with Cadence products used in the physical design and verification of integrated circuits. The IC SIG covers all aspects of physical design and verification for classes of integrated circuits including custom and semicustom, analog, mixed signal, and digital.

Cadence product families that are relevant to this SIG include:

  • Virtuoso Layout Editor and associated products
  • Diva, Dracula, Vampire verification
  • Device Level Editor
  • IC Craftsman
  • Place & Route products ( Cell3, Gate Ensemble, Cell Ensemble, etc)
  • HLD Physical DP products.

IC Special Interest Group 1998-1999 Top 10 Issues

  • A unified database for all verification tools is required. Integrate Diva, Dracula and Vampire into one verification tool. Improve RF extract (extract parasitic inductors).
    • Preliminary champion is Gerry Vandevalk from Nortel.
  • Data Management migration strategy is required. Customers would like to migrate to 4.4.x from 4.3.4 and have the same functionality without the TDM overhead. Currently tools only use the latest version of the data.
  • Better performance of IC Craftsman translation tool Echo is required. Currently it is very slow. Echo is the new interface between Artist and ICC. The old interface was considerably faster than Echo. It takes very long to translate even the smallest amount of data.
    • Preliminary champion is Shakil Siddiq from Nortel.
  • Roadmap and migration strategy for DP tools. Add support for recto-linear blocks.
    • Champion is Marie Kunesh from Texas Instruments.
  • Roadmap for the IC NT-tools is required. Will NT migration happen at the expense of other platforms?
  • Break down the cost of tool packages. It should not be necessary to pay for an entire tool if only a fraction of the functionality is desired. An option to create a customized tool package depending on the specific needs of the customer is required.
  • IC Craftsman cannot handle large amounts of data (cells/nets). Add the capability to use schematic-level constraints and cross-probe capability between ICC and Composer.
  • Performance and size of the psf files from circuit simulation needs adjustment. Compression of these files would create better performance. Integrate harmonic balance capability in Spectre.
    • Champion is Sue Strang from IBM.
  • Data in different releases of DEF is not compatible. The tool that writes data in DEF format may use a different version of DEF than the tool that reads in the data. Therefore, glitches may occur in the data transfer.
    • Champion is Wayne Miller from Symbol Technologies
  • Roadmap for Silicon Ensemble. Option required for the low-end user.