#6 Response: Standalone pin optimization tool?
IBM has developed their own pin optimization features and will present the results of their development at the ICU 2000. The presentation, X-Terminator: A hierarchical pin placement optimizer, is scheduled for Wednesday, September 13 @ 11:30 AM.
Current status: Cadence currently supports routing based pin optimization features when using Design Planner 3.4x and Cadence chip assembly router (Ccar) V5.0. together in a flow.
- Question?: Do customers want router based pin optimization features made available in Ccar as a standalone option?
Future status: Cadence has plans to implement pin optimization in future floorplanning products for both SP&R and Custom IC Layout.