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IC SIG - 2000 Top Ten Issues
- Cadence enablement in the development of verification files for foundry for tool acceptance. Specifically Assura files
for foundry customers such as TSMC, UMC, IBM.
Champion:
Michael Salcido, Boeing, michael.m.salcido@boeing.com
- Cadence to support a unified technology file in syntax and format and tools to generate the file rapidly for IC Craftsman,
Silicon Ensemble, the DFII.
Champion:
Emmanuelle Laprise, McGill Univ., emmanue@photonics.ece.mcgill.ca
- Support for generation and verification of manufacturer required pattern fill for quality metal variation on custom
chip designs.
Champion:
John Ellis, Cygnal Integrated Products, jwe@cygnal.net
- Performance of width wire routing in the Silicon Ensemble tool is poor. This is required for large data volumes which
cannot be routed in IC Craftsman.
Champion:
Di Phan, IBM, di@fishkill.ibm.com
- DIVA parasitic accuracy. Specifically inductive types of properties for smaller, high frequency devices. A 3-D algorithm
for parasitic coupling is required.
Champion:
Gerry Vandevalk, Nortel Networks, van@nortelnetworks.com
- Standalone pin optimization tool without the DP tool.
Champion:
Keith Barkley, IBM, barkleyk@us.ibm.com
- Option for low end user for the Assura tool. Assura verification required for small chip or macro level checking at
a lower cost.
Champion:
Sue Strang, IBM, sstrang@us.ibm.com
- Cadence to support third party plug in for the AMS simulation tool.
Champion:
Robert Burns, Motorola, rxsc60@email.sps.mot.com
- Early access to the Genesis database to enable migration of custom Early documentation is required.
Champion:
Michael Nicewicz, IBM, nicewicm@us.ibm.com
- Quality flow testing for ISR/QSR releases including
documentation on install paths.
Champion:
Donna Ducharme, Unitrode, ducharme@unitrode.com
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