1999 System and Circuit Design Top SIG Issues
- Provide change and modify after global find capabilities to ConceptHDL.
Champion: Al Craver (Acraver@GI.com)
Status: To be resolved in PE14.0
- Provide revision control of symbols used in schematics.
Champion: Al Craver (Acraver@GI.com) Control of the revision
Status: To be resolved Post PE14.0
- Provide physical part table and schematics synchronization capabilities
Champion: Al Craver (Acraver@GI.com)Since "packager" requires exact matching of "key" PPT properties, any changes made to global PPT files results in errors during packaging of a design that may have packaged successfully the day before.
In order to "add value" to a PPT file, designs are put at risk of failing packager. What is needed is a utility that will automatically update key properties on the schematic so that they match key properties in the PPT file.
A PPT update utility is needed that will allow updating of an archived PPT file. The current methodology is to just overwrite the archived PPT files, which defeats the purpose of archiving the design, which is to isolated the design from unwanted changes.
Status: To be resolved in PE14.0, will require a contraints property
- Provide better Openbook documentation for ConceptHDL.
Status: In PE13.6 there will be PDF Files, a Front to Back Methodology Guide and a basic tutorial on-line
- Provide "downrev" capabilities for schematics and symbols in ConceptHDL.
Or create a linked SCALD structure to the existing Concept-HDL library structure
Champion: Harry Bartley (harryb@mdhost.cse.tek.com)
Status: PE13.6 will support copy or linking of files in HDL Structure to SCALD structure
- Provide power and ground utility for assigning hidden power pins
Champion: Harry Bartley (harryb@mdhost.cse.tek.com)
Status: Tentatively scheduled for PE14.0
- Provide command to write all modified designs
Champion: Harry Bartley (harryb@mdhost.cse.tek.com)
Status: To be resolved in PE14.0
- Provide better and more descriptive error message documentation for Packager-XL.
Champion: Harry Bartley (harryb@mdhost.cse.tek.com)
Status: To be resolved in PE14.0
- Simulation resolve of units of measurements.
Champion: Al Craver (Acraver@GI.com)
The simulation tools need to provide an improved method of handling (UOM) units of measures. For example temperature coefficients for capacitors often use NPO,Y7R,COG, etc., but the simulation tools don't know how to decipher these.
Status: Part of AWB/PSPICE Integration
Another example is tolerance and wattage for resistors, these parameters are defined with % and W(watt) units of measure. If you try to pass tolerance as a value with its UOM, the simulation tools will die. There are 2 options, the first is to pass values without the UOM and the second is to modify the sim models that Cadence provides. The problem with the first solution is that it is common practice to attach properties to the schematic, with an associated UOM. Without the UOM, the property and its value must be displayed so that someone looking at the schematic knows what they are looking at. The problem with the second solution is that every time Cadence sends out a new release of tools, these sim models are overwritten. Obviously, copies can be made of the file, but it is a headache to restore all these files and the associated checks that need to be ensure things went as planned. One possible solution is to provide a user definable ASCII mapping file that the tools can read that provides conversion information.
- Support for Solaris 2.6 & Solaris 7 in PE13.5 Release
Status: PE13.5 & PE13.6 will support 2.6, PE13.6 will support 2.7- external dependency
- Need user settings for project file so project file does not change
Keeping 1 project file for the design, but allowing user changes in their own project file
Status: Scheduled for PE14.0 will require major changes
- Add Transcribe for ConceptHDL
Champion: Andy Jones (andy.d.jones@lmco.com)
Status: Scheduled for PE14.0
- Add read & write ASCII drawing file capability to ConceptHDL.
Status: Supported in current release
- Provide support for the "For Generate" and "If Generate" VHDL constructs in Concept-HDL and Packager-XL.
Champion: Andy Jones (andy.d.jones@lmco.com)
Status: VHDL package support under development
- Constraints Manager Support in Concept HDL
Champion: Michael Bowe (michael.s.bowe@intel.com)
Status: Scheduled for PE14.0